Manasa Sree. N

Contact Number: +91-953******* acp5dt@r.postjobfree.com

OBJECTIVE:

Looking forward to build my career by utilizing all opportunities to implement my skills and knowledge in order to pursue a long term relationship with the organization

WORK EXPERIENCE:

4.5 years of experience in Mobile System Testing and Multimedia application testing.

SUMMARY OF EXPERTISE:

Well versed with software QA Testing procedures, Test cases Preparation, Test plan execution

Specific expertise in Manual (Functional and GUI) Testing

Hands on experience in Smoke, Regression and Stress testing

Identification of Bugs through testing

Preparation of testing reports

Creating documents related to testing and their maintenance

Good knowledge of Testing methodologies and processes

EDUCATION:

Pursuing M.Tech in VLSI Design and Embedded Systems from V.T.U (waiting for results) with aggregate of 71% (till date)

Received Bachelor’s Degree in Electrical and Electronics engineering from J.N.T.U, Hyderabad in 2006 with an aggregate of 76.6%

Completed Intermediate from Board of Intermediate Education in 2002 with 93%

TECHNICAL SKILLS:

EDA Tools : Mentor Graphics, Xilinx

Languages : C, MATLAB

HDL : Verilog

Mobile OS : Android, Windows mobile 5/6, Symbian

Operating Systems : Windows

ACADEMIC PROJECTS:

Project 1: FPGA Implementation of Separable Reversible Data Hiding of AES Encrypted Data

In Separable Reversible Data Hiding technique, encrypted secret data is placed into encrypted image and exactly recovered back. This is possible by reserving space for secret data before encrypting cover media using reversible data hiding algorithm. Now, the data hider’s job is to place the secret data into the reserved memory space such that cover media and secret data can be retrieved separately only by the authorized ones. In the proposed project, AES encrypted data is placed into the encrypted image. LSB substitution reversible data hiding technique is used. Proposed system is coded in MATLAB for software proof of concept and is also coded in Verilog for FPGA implementation.

Project 2: Implementation of Forced-stack Technique in SRAM Cell

A 10T SRAM Cell is designed using Mentor Graphics tool.

About 10.5% of power reduction is observed with the designed 10T SRAM Cell when compared with the conventional 6T SRAM cell.

PAPER PRESENTATION:

Paper entitled “Separable Reversible Data Hiding of AES Encrypted Data” was presented in 2nd International Conference on Advances in Computer and Communication Engineering at Vemana Institute of Technology which is published in IJIRCCE.

PERSONAL SKILLS:

Passionate about ASIC Design, Physical Design and Embedded Systems

Comprehensive Problem Solving skills

Ability to deal with people diplomatically

Willingness to learn new technology

Excellent analytical capabilities, self-motivated, quick learner

PERSONAL INFORMATION:

Languages : English, Hindi & Telugu

Gender : Female

Marital Status : Married.

- Manasa Sree.

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