SHAIK MAHAMMAD AKRAM

FPGA DESIGN ENGINEER

Objective:

To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design.

Area of specialization :

FPGA Design Flow and Synthesis.

Summary in short:

Have got more than 10 months of experience in the field of FPGA Design.

Worked on Libero Soc tool for 2 months.

Worked on MATLAB, for generating HDL code from MATLAB.

Moreover i have done my academic project in physical design (CADENCE virtuoso tool).

Professional Experience:

ARKS MicroElectronics Pvt Ltd

July-2014 till date

FPGA Design Engineer

Responsibilities :

Logical design

Writing VHDL codes for various Designs.

Writing Test benches for designs.

Professional Training:

Undergone training on FPGA design flow (logical design) and HDL coding for circuit implementation and test bench, simulation, synthesis.

Projects carried out:

Blast pressure data controller and recorder

Client : HEMRL (High Energy Materials Research Laboratory) Pune

DESCRIPTION: There are mainly five units in the project, namely control unit, micro controller, FPGA unit, ADC and SRAM module. The control unit controls the start, stop, reset. FPGA is used for address generation, ADC serial configuration and synchronization in address, SRAM channel selection, SRAM chip selection. My job is to write VHDL code for achieving all the above.

Under water acoustic modem

Client : Naval science and technological laboratory (NSTL) Visakhapatnam.

DESCRIPTION: My job is to establish UART with low baud rate from 10 to 300bps using FPGA.

Study projects:

Frequency generator

DESCRIPTION: objective of this project is generating signal of different frequencies selected by the user (through PC using UART).

Brightness control:

DESCRIPTION: objective of this project is to control brightness of seven segment display using PWM technique

Time display

DESCRIPTION: objective of this project is to display time in seconds, minutes, and hour’s format using seven segment displays.

Curriculum project

Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits.

DESCRIPTION: Objective of the thesis is to optimize the power consumption of VLSI circuits that too particularly leakage power. Discovered a new technique to reduce average power consumption by 60 to 65% and leakage power consumption by 80% with negligible area and delay overhead.

Tools used:

CADENCE Virtuoso for physical design

CADENCE NClaunch for logic design using VERILOG

Xilinx 13.2, Xilinx 10.1 for a period of 6 months

Libero Soc v11.4 for a period of 2 months

MATLAB (VHDL code generation from matlab)

Curriculum Details:

10th Matriculation 2004 -2005 75.6%

Higher Secondary 2005 -2007 80.1%

B.Tech in Electronics and Communication 2007 -2011 (Affiliated to JNT Kakinada University, AndhraPradesh).

M.Tech in Embedded systems and VLSI Design 2011-2013 71.52% (gayatri vidya parishad college of engeneering (Autonomous))

Published two international journals.

Skills:

Hardware languages: VHDL, VERLOG.

RTL and Behavioral.

Strong in digital concepts.

Software languages: Basic C.

Operating Systems: UNIX, Windows.

Script Language: Basics of Perl, UNIX Shell Scripts.

Key Strengths:

Time Conscious.

A go-getter.

Quest for perfection in all assignments.

Personal Details:

Date of Birth: 11-06-1990.

Language Known: Telugu, English, Hindi.

Nationality: Indian.

Marital Status : Single

References: will be provided on request.

Contact this candidate