SHIKHA K PADMAKSHAN

**** * ********** *****, *** #2007, Tempe, AZ -85281 Ph: 480-***-**** e-mail: acozvk@r.postjobfree.com

Linkedin URL: www.linkedin.com/in/shikhapadmakshan

Electrical Engineering Graduate student specializing in Digital Circuit Design. Experienced in RTL Design and verification,

synthesis, Layout optimization, HSPICE simulations and Static Timing Analysis. Worked on full-custom designs and automated

designs including Register Files and L1 Cache for low power constraints and 32-bit MIPS processor. Seeking full-time opportunities in

SoC or ASIC design and verification.

EDUCATION

Master of Science in Electrical Engineering, Arizona State University, Tempe, AZ GPA: 3.58/4.0 May 2015 (Expected)

Courses: Digital Systems and Circuits, VLSI Design, Advanced VLSI, Hardware Design and Verification Languages, Computer

Architecture, Advanced Analog Integrated Circuits, Digital Signal Processing, Technology Computer Aided Design.

Bachelor of Engineering in Electronics and Communication, Anna University, Chennai, India GPA: 8.55/10.0 May 2013

Courses: Electronic Circuits, Linear Integrated Circuits, Microprocessors and Microcontrollers, Computer Architecture & Organisation

TECHNICAL SKILLS

Design and Layout tools - Cadence Virtuoso, Cadence Schematic and Layout Editor, Spectre, Synopsys Primetime,

NanoTime, SoC Encounter, HSPICE, Tanner EDA, Agilent ADS

Scripting languages -Perl

Programming Languages - C, C++, Java

Hardware Languages - Verilog HDL, SystemVerilog

HDL Tools - Aldec Active HDL, Aldec Riviera Pro, Xilinx ISE

Simulation - Matlab & Simulink, Silvaco Atlas (Deckbuild, Devedit, Tonyplot), Pspice

Operating Systems - UNIX, Windows 98/2000NT/XP/Vista/7/8, Mac OS

ACADEMIC PROJECTS

Digital Circuit Design

1. Design of a 1GHz Cache Memory using Cadence Design Suite (Technology: Synopsys 32nm) Fall 2014

Designed and implemented an 8KB, 4-way set-associative L1 cache with peripheral circuitry including a differential sense amplifier,

tag comparator, write buffers and decoders.

Performed sense amplifier mismatch analysis and offset voltage determination using HSPICE

Modern SRAM layout with independent tag and data array. DRC and LVS were performed using Hercules VUE.

Verification and delay analysis using a 4-corner model. Static Timing Analysis was done using NanoTime.

2. 32x128 Byte-writable Register File Design using Cadence Design Suite (Technology: Synopsys 32nm) Fall 2014

Designed bitcell with one read port and one write port along with input/output and control circuitry including decoders, set -

dominant latch, pre-charge and keeper circuits and write-drivers.

Hierarchical layout design optimized to achieve minimum area and low power consumption.

Performed DRC and LVS using Hercules VUE.

Extracted the layout using StarRC, analyzed and verified using HSPICE test -benches at various process corners. Static Timing

Analysis using NanoTime.

3. RTL to GDSII and APR for a 32-bit MIPS processor (Technology: Synopsys 32nm) Spring 2014

Performed synthesis of the SystemVerilog code after verification using Cadence RTL Compiler.

Performed APR using Cadence SoC Encounter and did Static Timing Analysis using Primetime.

4. Standard Cell Design using Cadence Design Suite (Technology: Synopsys 32nm) Spring 2014

Design of a non-inverting buffer, multiplexer and latch with asynchronous reset for a standard cell library in accordance with the

predefined standard cell dimensions.

Aimed to achieve the design at minimum layout area. Performed DRC and LVS using Hercules VUE and the extracted netlist (using

Star RC) was used to drive various loads to make delay measurements.

5. Design of a One-Bit Full Subtractor (Technology: TSMC 240nm) Fall 2013

Circuit was designed using Cadence design suite with transmission gates to reduce the number of transistors and consequently

the Energy Delay Product while achieving minimum layout area.

Computer Architecture

1. Implementation and Analysis of Thread-Level Parallelism using C programming for Intel Core TM i5-3337U Processor Spring 2014

Implemented thread-level parallelism using POSIX threads and analyzed execution speedup and accuracy.

2. Determination of cache latency using C programming for Intel Core TM i5-3337U Processor Spring 2014

Determined and analyzed access latency for various levels of cache hierarchy taking into account the microarchitectural princ iple

of spatial locality and the role of TLB in virtual addressing.

RTL Design and Verification

1. Design and Verification of a memory controller for MIPS CPU in Verilog using Aldec Active HDL Spring 2015

Designed a memory controller interfaced with a 1KB RAM, a 1KB ROM, I2C and a 2KB SDRAM and performed verification of the integrated

design using a CPU BFM.

2. Design and verification of hardware for implementation of I2C serial bus protocol using Aldec Active HDL Spring 2015

Implemented State-Machines for I2C master and slave in Verilog along with synchronization of I2C clock domain with core clock domain.

3. Design and verification of an asynchronous FIFO, Register File, Data Memory and Instruction Memory in Spring 2015

SystemVerilog using Aldec Riviera Pro.

The modules were designed and verified using program blocks in SystemVerilog to achieve full code coverage, branch coverage and

expression coverage and high toggle coverage.

4. Design, Verification and Synthesis of a 32-bit MIPS Processor in SystemVerilog Spring 2015

Designed and Verified for a subset of the MIPS instruction set using Aldec Riviera Pro and Synthesized using Cadence RTL Compiler.

5. ALU Component Design and Verification in Verilog using Aldec Active HDL Spring 2015

Designed ALU components including a 4-bit Ripple Carry Adder, 16-bit Carry Select Adder, 16-bit Multiplier and a 16-bit shifter for signed

arithmetic. Implemented of Baugh-Wooley algorithm for two’s complement multiplication.

6. Implementation and Verification of hardware for a packet-based switch protocol in Verilog using Aldec Active HDL Spring 2015

Designed and verified a switch with an input interface, memory interface and an output interface with 4 output ports.

Radio-Frequency circuit Design

Design of RF front-end for Ultra Wide Band (UWB) multiband OFDM transceiver (Technology: PDK 90nm) 2012-13

Collaborated the design of Low Noise Amplifier, Mixer and Power Amplifier to build a transmitter-receiver unit for UWB communication

(3.1-10.6 GHz) using Agilent ADS to optimize input/output matching, gain, noise, linearity and reverse isolation.

Digital Signal Processing

Frequency-Domain Adaptive Noise Cancellation using Fast Fourier Transform in MATLAB Fall 2013

Implemented Finite Impulse Response filter that is adaptive in nature with respect to the error in the output as compared to the input

for noise cancellation.

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