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C, Verilog. Synopsys Design compiler, VCS compiler, Hspice. Xilinx ISE

Location:
Bengaluru, KA, India
Salary:
1.5 L
Posted:
February 20, 2015

Contact this candidate

Resume:

KARTHICK.C

+91-890*******

acod64@r.postjobfree.com

CAREER OBJECTIVE

My goal is to become associated with a company where I can utilize my skill and

creativity to achieve organization goals, gain personal experience while enhancing the

company’s productivity and reputation.

SUMMARY

A focused, determined individual working towards being up-to-date in the ever

changing Technology environment. A team player with ability to guide and lead team

members.

EDUCATION

2014 - M.E- VLSI Design from K.S.Rangasamy College of 6.8*

Technology

2011- B.E- ECE from Angel College of Engineering and 7.6*

Technology

2007 - Class 12 from Vivekananda vidhyalaya matric hr. sec. 75%

School

2005 - Class 10 from Vivekananda vidhyalaya matric hr. sec. 72%

School

*overall grade point average in scale of 10.

SKILL

Programming Language C, Verilog.

ASIC Design Tools Synopsys Design compiler, VCS compiler, Hspice.

Synthesis tool Xilinx ISE, MATLAB

Functional verification tool Modelsim.

PROJECT & PUBLICATION

Title SAR Image Segmentation Based on Superpixel Merging Algorithm.

My proposed algorithm is to obtain segmentation of the Synthetic Aperture

Objective

Radar (SAR) image and to reduce computational cost of the algorithm. It

uses superpixels as the basic operation units instead of pixel.

Publication International Journal of Innovative Research in Science, Engineering and

Technology (IJIRSET)- 2014

AWARDS & ACHIEVEMENTS

• Attended workshop in Advance frontend ASIC Design using

Academic

Synopsys EDA tools.

• Certified Embedded Design Engineer (From Accel IT Academy)

Presented a paper titled “Context based hierarchical unequal

Co-curricular

merging algorithm in NCRTICE” -2014.

Attended a national seminar on “Research Application Using

MATLAB” in Kongu Engineering College 2014.

Won 2nd prize in national level technical symposium for paper

presentation on “Embedded System Based Train Detail

Provider”-2010

Presented project in 12th Indian Society for Technical Education

Convention -2009.

Attended training program about GSM & WIFI in BSNL.

Extra- Organized National level workshop on VLSI Design in 2010.

Curricular Organized a project fair in National level Technical Symposium

at ACET in 2009.

Award of Appreciation Certificate in programming contest,

Quiz, Paper Presentation.

INTERESTS

Playing Kabadi, Listening to music

PERSONAL DETAILS

No: 37, 2nd, street,

Address

Seethalakshmipuram,

Gobichettipalayam, Erode, Tamil Nadu. Pin-638476.

Date of Birth 11th December 1989

English,Tamil

Languages

I hereby declare that all the details furnished above are true and correct to the best of my

knowledge and belief.

Karthick .C



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