Seshank Varma

Email id: acoc3m@r.postjobfree.com

Mobile Number: 735-***-****

Career Objective:

To seek a challenging environment that encourages continuous and

research oriented approach of learning where I can utilize my skills.

Core Competency:

Good understanding of fundamentals of Transistors and circuit theory

Good knowledge of Verilog RTL coding

Good knowledge of Digital Design Concepts

Good exposure to technology by undergoing additional training in VLSI

Implemented a VLSI project during my undergrad

Attended technology intensive courses conducted by industry experts on

VLSI

Good working knowledge of Linux

Education :

Degree

Discipline

Institute

University

Year of Passing

Aggregate

ME/M.tech

Microelectronics

Manipal Institute of Technology

Manipal Academy of Higher Education

2015

CGPA 9.03/10

BE/B.Tech

Electronics & Communication

Drk College of Engineering and Technology

Jntu Hyderabad

2013

76.96 %

12th

Narayana Junior College

AP State Interboard

2009

93.5 %

10th

Nskk High School

SSC

2007

83.16 %

Academic Projects:

Title: Design, Implementation and Validation of Bridge Logic for

Intel's Next Generation Display Phy IP

Role: RTL Intern

Organization Intel India

:

Duration of 12

Project in

Months:

Description: Project Work Deliverable's:

1. Bridge RTL

2. New Display Phy Family (Phy + Bridge)

3. Test Environment, Test-Suite Phy + Bridge Validation

4. Interoperability Testing Environment & Test-Suite for

Phy + Bridge + External Controller

5. Timing Constraints for Bridge

Tools Used : Vcs, Synopsys DC Compiler, Questa CDC

Challenges Delivering IP with quality

Faced:

Title: Design of Embedded Data Acquisition System in Verilog HDL

Role: Team Lead

Organization Drk College of Engineering

:

Duration of 6

Project in

Months:

Description: Project Deliverable's:

1. Asynchronous FIFO Design Considering Synchronizers

2. I2C Bus

Tools Used : Modelsim

Challenges Developing Testbench Environment to cover maximum

Faced: functionalities, Understanding I2C and Asynchronous FIFO

Design Failures in Post Silicon

Title: VIP Development for AXI Protocol

Role: Team Member

Organization VLSI Guru Institute

:

Duration of 3

Project in

Months:

Description: Project Deliverable's:

1. Implementing Monitor, BFM, Checker, Assertions.

2. Functional and Code Coverage

3. Developing Test-Suite

Tools Used : Questasim

Challenges Understanding OOPS Concepts of System Verilog, SVA, and

Faced: Understanding AXI Protocol.

Skill Set:

Tools: Cadence(Virtuoso schematic and Layouts),DRC,LVS,NC Sim,

Modelsim, Questasim, Xilinx ISE 10.1, Atrenta Spyglass,

Beginner in Encounter tool, Worked on Monte Carlo Analysis

and Corner Analysis, Spectre Simulator, Questa CDC,

Atrenta Spyglass

Languages: C, Verilog, System Verilog, SVA, Fundamentals of VHDL,

Bash shell Scripting, Perl Scripting, UPF.

Work Experience:

Organization Intel

:

Designation: RTL Intern

Duration of June 2014toApril 2015

Project in

Months:

Organization Karnataka Microelectronics

:

Designation: Analog Layout Intern

Duration of Sep 2013toApril 2014

Project in

Months:

Achievements:

Gate-2013 qualified with 96 percentile

Secured third place in Mtech-Microelectronics batch for the academic

year 2013-2014

Secured first place in poster presentation on "ORGANIC LEDS"

Personal Profile:

Name

: D Seshank Varma

Date of Birth

: 8/June/1992

Address

: Bellandur, garudadri residency,bangalore - 503603

Father Name

: DBTS Rama Raju

Nationality

: Indian

Sex

: Male

Languages known

: English, Hindi, Telugu

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