SHARATH S VENKATESHA

acob9m@r.postjobfree.com

Summary:

• 2.5 years of professional experience with 6 months of experience as a Design Engineer at SSR Labs.

• Good understanding of concepts related to CMOS VLSI Design, ASIC Design and Verification, Physical Design.

• Proficient in Logic Design, Synthesis and Static Timing Analysis.

• Experience with Cadence and Synopsys tools like Virtuoso, Encounter, Design Vision, HSPICE, PrimeTime and

TetraMax.

• Hands-on experience with concepts such as DRC, LVS, PEX/RCX, floor-planning, automatic place and route.

• Good understanding of concepts such as Design For Test, Built-In Self Test, fault analysis, fault simulation and tools

related to these such as TetraMax for ATPG.

• Good programming skills in Verilog, VHDL, System Verilog, C/C++ and scripting in Perl.

• Proficient in Computer Architecture concepts like Pipelining, Caching, Memory hierarchy and Cache Coherency.

Education:

• Master of Science in Electrical Engineering (Digital Systems) May 2014

The University of Texas at Dallas (UTD)

Core GPA: 3.6/4.0

• Bachelor of Engineering in Electronics & Communication Engineering June 2010

Visveswaraya Technological University (VTU)

Percentage: 74.66%

Skills:

Programming : C, Verilog, VHDL, Perl, System Verilog.

EDA Tools : Xilinx ISE, TetraMax (ATPG), Design Vision, HSPICE, Cadence Virtuoso, Primetime(Static

Timing Analysis), Encounter (Place and route), MATLAB, Simulink.

Others : Unix, Networking.

Work Experience:

Scalable Systems Research Labs, Inc August 2014 – Present

Design Engineer (Verilog RTL Design)

Responsibilities

• Design of Floating point multiply unit for 64-bit multiplication using Fused Booth Encoder Multiplexer.

• Implement a Wallace Tree for the addition of the partial product bits.

Environment: Verilog, Xilinx ISE, Vivado.

Infosys Limited, India September 2010 - July 2012

Systems Engineer

Responsibilities

• Completed training in Networking in INFOSYS LIMITED in February, 2011. Trained on network design and

configuration of network elements like switches and routers.

• Coordinated with the clients to maintain the environment (servers/databases/network).

• Analyzed the issues faced by the clients and helped them resolve it within the specified deadlines.

Environment: Unix, Bridge Clarify.

Relevant Coursework:

VLSI Design Advanced Digital Logic Testing and Testable Design Digital Signal Processing

Computer Architecture Microprocessor Systems Analog Integrated Circuit Design

Projects:

Design of 1k-bit SRAM June, 2014

• Designed a 1k-bit SRAM consisting of 6T memory cells, row and column decoders for address lines, sense amplifier

and write circuitry. The components were sized in order to obtain the best read and write times and optimal area.

• The layout of the SRAM was done in Cadence Virtuoso layout Editor using IBM 130nm process design rules.

• The Design Rule Check (DRC) and Layout v/s Schematic (LVS) check were carried out. The place and route was done

manually.

Environment: Cadence Layout Editor, Cadence Schematic Editor, HSPICE, Waveview.

Design of 20-bit Booth Multiplier September, 2013

• Implemented an 8-bit Booth multiplier algorithm in Verilog using Behavioral modeling. Used IBM 130nm process and

Cadence Design tools to design and layout INV, NAND2, NOR2, XOR2, MUX2:1, OAI3222 and AOI22 with minimum

area.

• Performed RTL synthesis of the Verilog code using Design Vision, verified their functionality using HSPICE

simulation and WAVEVIEW, Static timing analysis using Primetime and place-and-route using Encounter.

• A custom library was generated using Liberty NCX. ASIC design cycle from RTL to layout completion, was followed

in order to complete the Booth Multiplier chip design.

Environment: Verilog, Xilinx ISE, Design Vision, Cadence Schematic Editor, Cadence Layout Editor, HSPICE, Liberty NCX,

Encounter.

Testing of Digital Circuits April, 2014

• Modeled and implemented a simple Ripple Carry Adder and made it BIST-testable by adding an External-XOR LFSR

as pseudorandom pattern generator and a MISR as signature compressor in Verilog using Behavioral modeling.

• Performed synthesis using Synopsys Design Vision. Analyzed changes in area and delay for the circuit before and after

making it BIST-testable.

• Used TetraMax tool to find all stuck-at faults, test vectors (ATPG) and the fault coverage.

Environment: Verilog, Xilinx ISE, Design Vision, TetraMax.

Simulation of Elastic 2D Collision of Balls in a Non-rigid Frame April,2014

• Simulated kinetic behavior balls and their collisions with obstacles within a bounded area under the effect of gravity.

• The movement of balls was calculated using the basic laws of motion and projectile motion for movement after

collision with the obstacles. These calculations were made on the ARM Cortex M4 processor embedded on the Stellaris

Launchpad.

• The processor was programmed in C to do the required calculations.

• The calculated co-ordinates were sent to the PC using UART communication at a BAUD rate of 115200. These co-

ordinates were interpreted in GUI to show the movement of the balls in real-time.

Environment: C, Code Composer Studio, Eclipse, ARM Cortex M4 processor.

Performance Analysis of Different Branch Predictors April, 2013

• Explored the effects of different choices for branch predictors in the Alpha 21264 microprocessor. Analysis was done

using the Simple-scalar simulator.

• Since the simulation of the out-of-order model is slow, the first 1 million instructions were skipped and the next 10

million instructions were executed.

• In the first part, different types of branch predictors (Bimodal, 2-level and Combinational), with varying size of the

Return Address Stack (RAS), were compared and analyzed based on performance.

• In the second part, the performance of the Branch Target Buffer (BTB) was analyzed for different configurations

(Associativity).

Environment: Unix, Superscalar.

Cache Optimization February, 2013

• Fine tuned the cache hierarchy of an Alpha microprocessor for 3 individual benchmarks (gcc, anagram and go).

• Optimization was done using Simplescalar simulator.

• Given a two-level cache hierarchy, identified the optimal configuration in terms of achieved CPI for each benchmark.

• The entire process of obtaining the data and performing the calculations was automated by a Perl script.

Environment: Unix, Simplescalar.

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