*year experience at INTEL MOBILE COMMUNICATONS.

JAHNAVI : - +91-808*******

House no 62,3rd main : aco9m7@r.postjobfree.com

7th cross,rangappa layout

BSK 3RD STAGE 3RD PHASE.

bangalore-85.

CAREER OBJECTIVE:

1Exposure to large spectrum of front end design activities encompassing system verilog,

universal verification methodology.

2A self-motivated and result oriented focused professional with around 1 year of experience

in Backend VLSI domain at INTEL MOBILE COMMUNICATIONS.

3Hands on Experience in handling MBIST logic generation and verification, BSCAN

generation and verification with tools MBIST Architect and BSD Architect from

mentor graphics.

4Dedicated and confident with focus on quality, rapport as well as team and relationship

building.

5Technically proficient with proven ability to deliver on time.

TECHNICAL SKILLS:

Programming Languages C, C++, scripting language PERL.

Hardware Modeling Languages Verilog/Vhdl, system verilog, UVM verification.

Windows, unix.

Operating system

Tools Expertise MBIST Architect, BSD Architect.

Core Expertise MBIST generation & verification, BSCAN generation &

verification,UVM verification.

Simulators Questasim, Modelsim.

Area Of Interest Digital System Design &Verification,

Full Custom Design, ASIC.

Interested subjects Logic Design, Microprocessor, DFT.

WORK EXPERIENCE

Vlsi guru training center

Company

March 2013- dec 2014.

Duration

SV, UVM verification methodology.

Team Details

ASIC verification trainee(PCIe trainee)

Role

Intel Mobile Communication (IMC), India

Company

July 2011- July 2012.

Duration

Design For Testability (DFT), Team size :14

Team Details

Verification Engineer (Intern)

Role

PROJECT PROFILE:

Project – M.TECH projects.

“Electronic code lock”(using 8051 microcontroller)

Title

An electronic lock is a device which has an electronic control assembly attached to

it. They are provided with an access control system. This system allows the user to

unlock the device with a password. The password is entered by making use of a

keypad. The user can also set his password to ensure better protection. This project

describes the making of an electronic code lock using the 8051 microcontroller.

Description

The major components include a keypad, LCD and the controller AT89C51 which

belongs to the 8051 series of microcontrollers.

Involved in Design and Coding Phase.

Role

Implementation of electronic code locks system.

Aim

Project undertook during Internship project at Intel mobile commutations

Implementation of DFT concepts for testchip

Title

Project description: Design for Test (aka "Design for Testability" or "DFT") is a

name for design techniques that add certain testability features to a

microelectronic hardware product design. The purpose of manufacturing tests is to

Description validate that the product hardware contains no defects that could, otherwise,

adversely affect the product’s correct functioning.

MBIST logic generation and verification using Mentor graphics MBIST Architect

tool, BSCAN logic generation and verification using BSD Architect tool.

Role

Aim The aim of this project is the testing of various memory blocks and boundary scan

for the testchip of 28 nm technology.

Project undertook during ASIC VERIFICATION TRAINING

USB2.0 Core Functional Verification using UVM & System Verilog

Title

USB2.0 core is design that goes in to every USB2.0 based devices, acting as an

interface between Host and USB2.0 function controller. As part of this design

verification we have worked on complete flow of verification, starting from

feature listing down to coverage closure. We verified all supported features like

Description

speed negotiation, enumeration, data transfers, suspend and resume.

Listing down features, scenarios

Testplan development

Developing testbench architecture

Coding Testbench components including reference model and checkers

Role

Verification closure using Functional coverage & code coverage as closing

criteria.

Aim Verification using UVM & System Verilog

Project undertook during ASIC VERIFICATION TRAINING

AHB Interconnect Functional Verification using UVM & System Verilog

Title

AHB interconnect is configurable design for connecting multiple masters to

multiple slaves. Design also has a configuration interface for configuring slave

address ranges. As part of design verification we verified interconnect for

Description different number of masters, slaves and slave address range configurations.

Listing down features, scenarios

Testplan development

Developing testbench architecture

Coding Testbench components including reference model and checkers

Role

Verification closure using Functional coverage & code coverage as closing

criteria.

Aim Verification using UVM & System Verilog

Project undertook during ASIC VERIFICATION TRAINING

AHB UVC Development

Title

AHB UVC component development for AXI2.0 protocol. As part of this project

we have developed Driver, Sequencer, Monitor, Coverage models. We have also

developed basic sequences targeting all features of AHB protocol.

Description

Listing down features, scenarios

Testplan development

Developing testbench architecture

Coding Testbench components including reference model and checkers

Role

Verification closure using Functional coverage & code coverage as closing

criteria.

Aim Verification using UVM & System Verilog

EDUCATIONAL PROFILE:

Year of Percentage

Examination Board Institution

passing

ASIC verification

trainee

Training completed

Vlsiguru institute Vlsiguru institute 2014

(PCIe training)

M.Tech

( VLSI Design and VTU Belgaum 75%

SJCE, Mysore. 2012

Embedded Karnataka

Systems)

SLN College of

VTU Belgaum 65%

Engg.,

B.E 2009

Karnataka

Raichur

Board Of

73%

Intermediate AME’S College,

P.U.C 2005

Education Raichur.

Karnataka

Board Of

Secondary

St. Mary’s School, 74%

SSLC Education 2003

Raichur.

Karnataka

I declare that the information given above is true to the best of my knowledge.

[JAHNAVI]

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