WEIPENG LI

** ******* ******, *** **, Ossining, NY, 10562

650-***-**** (cell), aco00b@r.postjobfree.com

EDUCATION:

Yale University, New Haven, CT, USA

Ph.D. in Department of Electrical Engineering

March 2007

Thesis title: MIS structures based on GaAs and GaN

Advisor: Professor T.P. Ma

Tianjin University, Tianjin, China

B.S. in Department of Electrical Engineering

July 2001

GRE: 2400 (800/800/800), Full Score

EXPERIENCE:

Lead Financial Strategy Analyst, IBM, Software Defined Storage Global FP&A,

NY April 2012 ~ Now

. Led the development of the brand global 3-year Strategy and annual

Budget, analyzing market research, revenue, gross profit, headcount,

route-to-market, business partner investment, product roadmaps,

business intelligence, risks, capital, and P&L, coordinating

Development, Product, and Sales teams, and prepared the Finance Vice

President and the General Manager for IBM CFO review.

. Proficient in Python programming and Excel, SPSS statistical analytics,

including regression, clustering, correlation, time series and testing

of statistical hypothesis; Proficient in database query (Brio, SQL) on

large amount of data.

. Project manager for the end-to-end world-wide Finance IT System

transformation, with Agile methodology, starting from requirements

gathering, defined and reengineered processes, guided the software

engineers and financial analysts across the world, communicated with

multiple stakeholders, overcame obstacles, and delivered system on

schedule.

. Developed the monthly and quarterly P&L reporting and forecast with

proper reporting and forecasting methodologies.

. Supported Sales Operations team on analysis of revenue trends and key

drivers, productivity, incentives, performance improvement programs,

reorganization, and resource allocation.

. Screened acquisition candidate companies on financial performance, with

DCF valuation.

. Led the Acquisition Integration of a company-Storwize, and reviewed

with the Board of Directors.

. Invented a portfolio ROI prioritization methodology and convinced Vice

Presidents to implement.

. Created the strategic competitive intelligence assessment on EMC and

Netapp.

. Drove the Cloud, Big Data, SaaS transformation and Utility model

adoption on both HW and SW.

Pricing and Investment Specialist, IBM, Power Brand Global FP&A, NY

January 2010 ~ April 2012

. Developed the High Performance Computing (HPC) business case P&L for

investment ROI analysis, including IRR and NPV, annual Budget and 3-

year Strategic Planning.

. Forecasted the monthly and quarterly P&L.

. Guided sales/marketing teams on HPC systems RFP responses, designing

pricing structures, scenarios, and strategies, with competitive

analysis and sensitivity analysis.

. Supported Product Managers on product life-cycle management, including

End of Life management.

. Developed detailed costing analysis on HPC systems.

Lead Device Engineer, IBM, Semiconductor division, NY

April 2007 ~ January 2010

. Led teams of more than 10 engineers, including technology partners,

customers, and vendors, to design state-of-the-art transistors and

circuits, employed structured problem-solving technique, analyzed

immense data to identify trends, and made recommendations to develop

the cutting-edge digital, analog and memory technology at 32nm, 28nm

and 20nm nodes.

. Project manager for advanced Semiconductor reliability qualification

using waterfall methodology with Kanban, managing project schedule,

wafers starts, process splits, and reliability targeting, coordinated

with reliability and partner teams on resources, removed roadblocks,

and successfully delivered products on time in 1 year. Made a critical

decision to manage risk, saving $500,000.

. Proficient in SAS statistical analysis.

. Developed competitor semiconductor process-performance assessment,

including costing analysis, with expertise in semiconductor process

flows, modules and equipment, and with experience in the operation of

semiconductor fabs.

. Published 4 technology papers at premier international conferences,

with 9 US patents granted.

Research Assistant, Yale University, New Haven, CT

September 2001~ March 2007

. Developed a GaAs enhancement mode transistor, which demonstrated, for

the first time in the past 50 years, that inversion can be formed from

un-pinned p-GaAs by ex-situ deposited gate dielectric.

SOFTWARE and SYSTEMS:

. Proficient in Python, SAS, Excel, Essbase, Cognos TM1, SQL, applied

statistical analysis, data structure & algorithm design, and Cloud

architecture design, Knowledge of C, R, Tableau, Hadoop and Mapreduce.

PATENTS:

. US8445969, High pressure Deuterium treatment for semiconductor/High-K

insulator interface.

. US7893502, Threshold voltage improvement employing Fluorine and

adjustment Oxide layer.

. US7867839, Methods to reduce threshold voltage (Vt) in Silicone

Germanium (SiGe), High-K Dielectric-Metal Gate, P-Type Metal Oxide

Semiconductor Field Effect Transistors

. US7883953, Method for transistor fabrication with optimized performance

. US8106462, Balancing NFET and PFET performance using straining layers

. US8237197, Asymmetric Channel MOSFET

. US8298897, Asymmetric Channel MOSFET

. US8563394, Integrated Circuit structure having substantially planar N-P

step and method of forming

. US8623714, Spacer protection and electrical connection for array device

SELECTED PUBLICATIONS:

. W. Li, M. Hamaguchi, et al, "New Layout Dependency in High-K/Metal Gate

MOSFETs", IEEE International Electron Devices Meeting (IEDM) 2011,

24.6. Washinton, DC.

. J. Han, W. Li et al, "Cost Efficient Novel High Performance Analog

Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology

and Beyond", 2010 International Conference on Solid State Devices

and Materials, Tokoyo, Japan, C-6-5L, 2010.

. D. -G Park, W. Li et al, "High-k/Metal Gate Low Power Bulk Technology -

Performance Evaluation of Standard CMOS Logic Circuits, Microprocessor

Critical Path Replicas, and SRAM for 45nm and beyond," 2009

International Symposium on VLSI Technology. Systems, and Applications,

VLSI-TSA, pp.90-92.

. W. P. Li, J. F. Zheng, W. Tsai, X. W. Wang, and T.P. Ma. "Demonstration

of enhancement-mode GaAs metal-insulator-semiconductor field effect

transistor with channel inversion using Si3N4 as gate dielectric",

Appl. Phys. Lett. 92, 232904 (2008)

. W.P. Li, Sharon Cui, Yanxiang Liu, S. Shim, T. P. Ma. "Demonstration of

unpinned GaAs surface and surface inversion with gate dielectric made

of Si3N4", Applied Physics Letters, Appl. Phys. Lett. 90, 193503 (2007)

. W. P. Li, T. P. Ma. "Unpinned GaAs Metal-Insulator-Semiconductor with

Low-Temperature Grown Surface", Applied Physics Letters, Appl. Phys.

Lett. 89, 233514 (2006).

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