Bharath reddy bhimavarapu

Mobile: +91-990******* E-Mail id: acn457@r.postjobfree.com

To be attached with a successful organisation and get trained form the best people and do

my best for the growth of the organisation and my self.

Academia

Discipline / Percentage Year of

Sr. No. Course Board / University

Specialization Passing

1. M.Tech VLSI Design VIT University 75 2014

Electrical & electronical

2. B.E. JNTU University 70 2012

engineering

State Board Andhra

3. inter Mpc 85.7 2008

Pradesh

4. SSC SSC andhra State Board 81.00 2006

TECHNICAL SKILLS

1. VLSI Tools Cadence (virtuoso, encounter, RTL compiler).

2. Scripting languages Perl

3. Hardware Description Languages Verilog, System Verilog

4. Programming Languages C, Java,c++,jsp,servlet,html.

VLSI design skills

1. Good knowledge on architectures of ancient computations. (which are used to design the archetectures of high

speed Multipliers etc).

2. Low Power Analog Circuit design(Fine Grain Power Gating ).

3. Good knowledge on OP-AMP designing to reach the specifications easily.(By locating the poles and zeros of the

circuit and estimating the variation of gain with respect to variations in parameters).

4. Very good knowledge on desinging Filters,Amplifiers,and Multivibraters( both asstable and bistable)

5. Place and Route, bit file generation and implementation in FPGA for emulation.

6. Good knowledge and understanding of analog circuits and hands on experiance in analog layout design.

7. Basic knowledge of ARM and x86 architectures and programming.

Research and Projects

Project 1 (Published in SET VIT conference 2014)

Title : Fine Grain Power gating techniq used in a FPGA based design to attain optimum power

Date of start : June 2012 – November 2012

Description : we know FPGA(Field Programable Gate Array) consists of large number of LUTs. My project

is to to implement an Analog to digital (ADC) converter by send the LUT’S which are not in use into sleep

mode which reduces the Dynamic Power consuption. Tools used is XILINX ISE, and CADENCE

Project 2 (Published in SET VIT conference 2013)

Title : Block level Physical Design Implementation of Mixed signal ASIC full-chip using CADENCE

Encounter Tools:

Duration : December 2012- May 2013

Tools used : Cadence Encounter

Description: Complete design and timing closure from verilog netlist to routed design. Floorplanning,

power network synthesis, placement, clock tree synthesis, routing and the timing closure have been done

done single-handedly for the given block of an ASIC full-chip overcoming trans-cap-net-length violations,

timing, congestion issues etc.. All of this has been done in a live project using Cadence tools in the 45nm

technology.

PG Project3

Title : Delay Locked Loops(DLL)in ultrasonar sound systems

Duration : June 2013 –September2013

Tools used : Cadence RTL Compiler, Xilinx

Description : Design of Delay locked Loops upto 60 cycles,which are highly used in ultra sounding

image sensing systems . Tools used are xilinx, cadence . It is used in medical field.

PG Project3

Title : Low Power FIR Filter using Computational Shared Multiplier(CSHM) & low power ADC

Duration : November 2013 –May 2014

Tools used : Cadence RTL Compiler, Xilinx

Description : CSHM is used to avoid multiple multiplications by SELECT and SHIFT the values of pre

computer . Hence we can fetch the Pre computed values with high speed and also efficient. By using

VEDIC Multiplier the speed is still increased,this VEDIC Multiplier is derived from VEDIC Mathematics .

By using these multipliers FIR Filter is designed with high speed.

UG Project:

Title : Control Strategies for Distribution Static Compensator for Power Quality Improvement

Duration : Aug’11 – Apr’12

Tools used : Matlab

Description : Used to improve the Power Quality improvement by inducing capacitence effect to the cicuit

inorder to reduce inductance effect in the circuit.

ACHIEVEMENTS

1. Secured “Best student award “in VITHARVA’12 at VIT, Chennai.

2. Two times GATE Ranker in the stream of electrical and electronics.

3. Winner of the seminar competition based on ‘WITRICITY’ at NAGARJUNA UNIVERSITY '12.

4. Awarded as Best Outgoing All-rounder Student at QIS College of Engineering, ONGOLE

5. Secured 2nd rank in debate 2011 (Renewable Energy Resources) at QIS, ONGOLE.

6. secured 1st in RAMANUJA Mathematical Qiz at my 10th

EXTRA-CURRICULAR ACTIVITIES

1. Captain of college cricket team (winners of district tournament ) for the year 2011-12.

2. Organized the ‘Micro Mania’ Competition successfully at the National level technical event

‘QISFEST2K11’ held at Qis College of Engineering, Ongole.

PERSONAL VITAE

Date of Birth : 25th August,1990.

Address (Per.) : 3/11, prodduturu(po), kankipadu(md), krishna (dt)

State – andhra pradesh

Alternative email ID : acn457@r.postjobfree.com

Languages Known : English, Hindi and telugu

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge and

understanding.

Bharath reddy bhimavarapu

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