Mahendra K R

#**,******* ******,******,

Bangalore Email: acn2mk@r.postjobfree.com

Karnataka, India –560064 Mobile: +91-814*******

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Extensive experience in writing RTL models in Verilog HDL and Testbenches in

SystemVerilog and UVM

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and

verification

VLSI Domain Skills

HDL: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification - SVA

TB Methodology: UVM

Protocols: AXI, AHB, UART, I2C, SPI

EDA Tool: Questasim and ISE

Domain: ASIC/FPGA front-end Design and Verification

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, ABV- SVA

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

Bachelor of Engineering, Sri Revana siddeshwara institute of technology

Visvesvaraya Technological University, Karnataka, India

Discipline: Electronics and Communication Engineering

Percentage: 59%

Year: June 2014

Achievements

Good performer from Maven Silicon during the VLSI Design course

Good team member

Experience

Project Intern, Maven Silicon

Six months experience in front end design and verification

VLSI Projects

[1] Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of

the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

[2] GPIO – Verification

HVL : System Verilog

TB Methodology: UVM

EDA Tools: Questasim

Description: General purpose I/Os used in SoC

Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Engineering Project

Embedded design for smart irrigation system

Thank you

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