Prasad Pattadakal

Email id: acn25p@r.postjobfree.com

Mobile Number: 897*******, 779-***-****

Career Objective:

Intend to build a successful career in the VLSI domain with growth

prospect and contributing my best to the company.

Core Competency:

Good understanding of CMOS fundamentals.

Basic knowledge of ASIC flow.

Excellent problem solving and debugging skills.

Good knowledge of Digital Design Concepts.

Good knowledge of Verilog RTL coding.

Good understanding of Object-oriented programming (OOP) concepts.

Basic knowledge of UART, ETHERNET protocols.

Skilled in HVL such as SystemVerilog and UVM.

Hands on experience on the Mentor Graphics QuestaSim & ModelSim

Simulation tools.

Hands on experience in Coverage Driven Verification (Code coverage and

Functional coverage) using SV and UVM.

Well versed in writing test plans, coverage plans and constrained random

test cases.

Good working knowledge of Linux, and C programming.

Work Experience:

Organization: Nanochip Solutions Pvt Ltd, Bengaluru.

Designation: ASIC Design Verification Engineer Trainee.

Duration: July 2014 to present.

Education :

Degree

Discipline

Institute

University

Year of Passing

Aggregate

PG Diploma

VLSI

RV-VLSI Design Center

-

--

BE

Electrical & Electronics

B.L.D.E.A's Dr. P. G. Halakatti College Of Engg & Tech, Bijapur

(Visveswaraiah Technological University)

2014

67.95 %

12th

PCMB

VB Darbar PU College, Bijapur

(KEA)

2010

59.67 %

10th

Vishwabharathi Model High School, Bijapur

(KSEEB)

2008

90.08 %

Academic Projects:

Title: Verification of Mini Uart using UVM.

Role: Verification Engineer.

Organization: RV-VLSI DESIGN CENTRE.

Duration of Project 3 weeks.

:

Description: Development of verification plan and UVM Testbench

Architecture for Mini Uart SOC Subsystem incorporated

with a Micro Uart core and a dedicated synchronous

Microprocessor bus interface. Implementation of TLM

interfaces in the testbench to have connections

between the verification components. Verification of

functionality with randomized and directed test cases

leading to maximum functional and code coverage.

Regression testing was done to increase the coverage.

Coverage results were reported.

Tools Used: Mentor Graphics QuestaSim 10.1C in Linux platform.

Deliverable/Challen Synchronizing the Output and Input monitors with the

ges Faced: serial output/input data due to presence of two

clocks to increase the Functional coverage.

Found Bug in the FSM of Transmit and Receive block of

Micro Uart, due to which it was unable to achieve

100% code coverage. Bug was reported.

Title: Verification of Synchronous FIFO using SystemVerilog

and UVM

Role: Verification Engineer

Organization: RV-VLSI DESIGN CENTRE

Duration of Project 1 week.

:

Description: Functional Verification of synchronous FIFO using

SystemVerilog and UVM. Development of the

verification plan and Testbench architecture

components such as driver, monitor, scoreboard.

Running different test sequences for write, read,

simultaneous write/read operations to achieve maximum

coverage.

Tools Used: Mentor Graphics QuestaSim 10.1C with Linux platform.

Deliverable/Challen Performed multiple iterations to achieve 100%

ges Faced: coverage.

Achievements:

Secured First rank to the school in 10th std with 90.08 percentage.

Secured first rank in Aptimizer (Circuit debugging event) at

TECHTRONIX-2012 held in our college.

Personal Profile:

Name

:Prasad Pattadakal

Date of Birth

: 9/June/1992

Address

:Prasad Nilaya, Plot no 17, Visveswaraya colony, Near Mallikarjun

Ashram,BIJAPUR - 586103

Father Name

: Shivanand Pattadakal

Nationality

: Indian

Sex

: Male

Languages known

: English, Kannada, Hindi.

Contact this candidate