Resume

Name: Kalidindi Vijaya Rama Raju

Email: acn24f@r.postjobfree.com Mobile: 91-088********

DOB: May 07, 1991 91-096********

Address: *-***, ******** ******, *********** (M),

R.R District, Telangana -501505.

EDUCATION

Degree University/Institute Year CPI/Aggregate

M.Tech (ICT) Dhirubhai Ambani Institute of Information and 2012-14 8.02/10

Communication Technology (DA-IICT),

Gandhinagar, Gujarat

B.Tech (ECE) K.G Reddy College of Engineering and Technology, 2008-12 78.03%

Moinabad, Telangana

Intermediate Narayana Junior College, Vanasthalipuram, 2006-08 90.80%

Telangana

Board of Intermediate

High School Hayathnagar Public School, Hayathnagar, Telangana 2005-06 77.66%

S.S.C

SKILLS

Areas of Interest Memory Circuit Design and Testing, Low Power Processor Design

Programming Languages Verilog HDL, Perl, TCL, C

Tools and Technologies Cadence Virtuoso, Encounter and RC, ModelSim, Active HDL, LT-Spice, Xilinx

Technical Electives Digital System Architecture, Low Power VLSI, VLSI System Design, Labs in VLSI

PROJECTS

Dynamic Reconfiguration of Cache Memories for Leakage Power Reduction (March,14 – June,14)

Guide: Dr. Amit Bhatt Team Size - 2

When an application uses a small part of the cache, then the idle portion

contributes to leakage power/energy. This idle portion is switched off using

power gating technique saving vast amounts of power. Tools used for this project

were Cadence RTL Compiler, Active HDL and CACTI.

RTL to GDS-II Flow of Numerically Controlled Oscillator (Jan,14 – Feb,14)

Mentors: Shanmukha, Manjesh, Ajith, Ginu (Cadence Design Systems, Bangalore) Team Size - 2

The front end and back end flow was performed for NCO design to understand

the intricacies of ASIC design using Cadence tools. It was implemented using 90nm

technology. Tools used for this project were Cadence RTL Compiler, Encounter

and NCsim.

Designing a 45nm Custom Library (Nov, 13)

Guide: Dr. Biswajit Mishra Team Size-3

A 45nm custom library was compiled by drawing the schematic, symbol and

layout of the basic gates such as NAND, NOR, XOR etc., MUX, D-latch and D-FF.

Tool used for this project was Cadence Virtuoso.

Dynamic and Leakage Power Analysis Tool Using C (Oct, 13)

Guide: Dr. Biswajit Mishra Team Size-2

A useful power analyser tool was developed which takes in the Verilog file and

the VCD file and calculates the total power (dynamic and leakage) consumed by

Each sub-module in the design. Tools used for this project are Modelsim and

Code blocks.

Generation, Benchmarking and Synthesis of a Superscalar Processor Using (Aug,13 – Sept, 13)

FabScalar Toolset Team Size-2

Guide: Dr. Amit Bhatt

FabScalar is a reconfigurable RTL generator. A 4-Issue processor was generated

and SPECint2000 benchmarks were run on it to assess the performance of the

core. Also, the core was synthesized. Tools used for this project were FabScalar,

Cadence RTL Compiler and NCsim.

HDL Implementation of the Issue Stage of an Out-Of-Order Processor (September, 12)

Guide: Dr. Amit Bhatt Team Size-2

An OoO processor was designed and implemented in HDL using Tomasulo

algorithm. Low power techniques were used to reduce power consumption.

Tools used for this project were Modelsim and Cadence RTL Compiler.

Optimal Supply Threshold Scaling for CMOS Circuits (Sep, 13)

Guide: Dr. Biswajit Mishra Team Size-3

Analysis was carried out on a ring oscillator circuit which had 11 NAND gates in

Inverter configuration. Activity factor was varied by varying inputs to the inverter

chains. Operation of the circuit in sub threshold region was studied. Tools used

for this project were LT Spice and MATLAB.

Positions of Responsibility

Teaching Assistant, Digital Logic Design (Jan, 14 – May,14)

Teaching Assistant, Basic Electronics (July – Dec,12 & 13)

Teaching Assistant, Introduction to Communication Theory (Jan, 13 – April, 13)

M.Tech sports representative and a Student Body Government member (July, 13 – Till date)

Class Representative in B.Tech. (Aug, 08 – May, 12)

Awards and Achievements

Was awarded “Best Outgoing Student(ECE)” and stood college 1st in 3-2 and 4-1 Semesters.

Participated in zonal Cricket and Volleyball Tournaments.

Won 1st Prize in Paper presentation in ”AVANCO”.

Cracked GATE-2011 with 98.03 percentile.

Interests and Hobbies

Playing Cricket, Volley Ball, Listening to Music, Interested in learning new things

Declaration: The above information is correct to the best of my knowledge.

Date: (K. Vijaya Rama Raju)

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