SRIRAMDAS PAVANI

Email: acn037@r.postjobfree.com

Mobile : +91-967******* / +91-998*******

CAREER OBJECTIVE

Seeking a challenging and responsible opportunity where I can utilize my

technical strengths and potentials in a professional organization to meet

employer’s expectations and improve my knowledge and skills for my career

growth.

EXPERIENCE & TRAININGS

Overall experience of about 1.5 years in frontend design and verification on

different ASIC and FPGA related design IP’s.

Worked as trainee (Intern) VLSI front end designer at Neoschip Technologies,

Hyderabad from August 2013 to April 2014.

Completed 6 months Professional Development program in VLSI from

Sandeepani School of VLSI Design, Bangalore from August 2012 to January

2013.

PROFESSIONAL SUMMARY

Experience of Test Coverage Closure Using Gold Mine using system Verilog.

Worked on Efficient Implementation of Accumulation in Finite Field over GF

(2m) and its Applications using Verilog coding.

Worked on ASIC Implementation of DDR SDRAM Memory Controller.

Worked on Data Transactions on System-on-Chip Bus Using AXI4 Protocol

Worked on Design architecture of PCI, PCIX Protocol.

Worked on analysis of Adaptive Viterbi Decoder for High Speed Applications.

Design and Test Function Generator and Frequency Counter on FPGA Spartan

3E Kit.

Mat lab Projects:

Defect Detection in Patterned Fabrics Using Modified Local Binary Patterns

using mat lab.

Worked on Implementation of High Performance Distributed arithmetic adaptive

FIR Filter using mat lab.

TECHNICAL EXPERTISE

EDA Tools: Modelsim, Questasim, ISE12.1, Xilinx ISE 14.1, Leonardo

spectrum,

Programming Languages: Verilog, System Verilog, Perl, Matlab, C and Data

Structures

Microcontrollers / FPGA: Spatarn6, Virtex 6, Spatarn 3E

Familiar Protocols: APB, PCI, AXI

Familiar OS: Windows, Linux

ACADEMIC CREDENTIALS

Completed Bachelors in Engineering (B.Tech) in Electronics and

Communications (ECE) in May 2012 from Aurora’s Technological and

Research Institute, JNTU, Hyderabad with an aggregate of 73%.

Completed Intermediate (Mathematics, Physics and Chemistry) from Sri

Aurobindo Junior College, Nalgonda, Andhra Pradesh in March 2007 with an

aggregate of 86%.

Completed Secondary School (SSC) at Vidyadayani High School, Ghattupal,

Nalgonda, Andhra Pradesh in March 2005 with an aggregate of 70%.

EXTRA CIRCULLAR ACTIVITIES

Participated in paper presentation in MICROCOSM’10 at Mahatma Gandhi

Institute of Technology in April 2010.

Volunteered AURA-2K11, a National Level Technical Fest at Aurora’s

Technological & Research Institute in March 2011.

Participated in technical talk on embedded systems conducted by Aurora’s

Technological and Research Institute in November 2011.

PERSONAL INFORMATION

Date of birth: 29-12-1989.

Sex: Female

Nationality: Indian

Marital status: Single

Place of birth: Nalgonda

Languages known: Telugu, Hindi and English.

Current address: 316-B,Sree UTOPIA Apartment

Kadubeesanahalli, Marathalli

Sarjapur outer road,

Bangalore 560013.

KEY PROJECTS EXECUTED

1. Title of the Project: Test Coverage Closure Using Gold Mine using system

Verilog language.

Description: An automatic assertion generation engine that uses data mining and

formal verification. Goldmine mines the simulation traces of a behavioral

register transfer level (RTL) design using a decision tree based learning

algorithm to produce candidate assertions. These candidate assertions are passed

to a formal verification engine.

Software Tools: Questa sim

2. Title of the Project: Efficient Implementation of Accumulation in Finite

Field over GF (2m) and its Applications

Description: finite field accumulator (FFA) is used further for the

implementation of serial/parallel polynomial- basis finite field multiplication and

bit-serial inter-conversion between polynomial basis representation and normal

basis representation over .

Software Tools: Xilinx ISE

3. Title of the Project: ASIC Implementation of DDR SDRAM Memory

Controller.

Description: This DDR controller is typically implemented in a system between

the DDR and the bus master. It consists of three modules, the main control

module, the signal generation module and the data path module. The main

control module has two state machines and a refresh counter, which generates

proper Istate and cstate outputs according to the system interface control signals.

The signal generation module generates the address and command signals

required for DDR based on istate and cstate. The data path module performs the

data latching and dispatching of the data between the bus master and DDR.

Software Tools: Xilinx ISE

4. Title of the Project: Data Transactions on System-on-Chip Bus Using AXI4

Protocol

Description: AXI is current generation bus protocol that overcomes limitations

of AHB and provides specification for a faster, more flexible interconnect

network of master and slave devices. Unlike AHB, in AXI multiple masters can

have transactions in parallel simultaneously depending on the implementation.

AXI does not specify the requirement or necessity of having an arbiter or

decoder. Masters and slaves can connect to interconnect.

Software Tools: Xilinx ISE

5. Title of the Project: Design architecture of PCI, PCIX Protocol.

Description: The PCI bus is a 32- or 64-bit wide bus with multiplexed address

and data lines. The standard operating speed is 133MHz, and data can be

transferred continuously at this rate for large bursts. The Peripheral Component

Interface (PCI-X) addendum is an enhancement to the current 64 bit 66MHz PCI

bus specification. PCI-X revised the conventional PCI standard by doubling the

maximum clock speed (from 66MHz to 133MHz).

Software Tools: Xilinx ISE

6. Title of the Project: Defect Detection in Patterned Fabrics Using Modified

Local Binary Patterns.

Description: A method for detecting textural defects in patterned fabrics based

on modified Local Binary Patterns has been presented The proposed method has

an acceptable detection rate (more than 95%) in all kinds of the defects which is

more than that of human experts.

Software Tools: Matlab.

7. Title of the Project: Implementation of High Performance Distributed

arithmetic adaptive FIR Filter.

Description: Filters play an important role for removal of unwanted signal or

noise from original input signal by removing the selected frequencies from

incoming signal. They became much popular due to the increase of the digital

signal processing. Adaptive digital filters are widely used in the area of Signal

processing such as echo cancelation, noise cancelation and channel equalization

for communications and networking systems

Software Tools: Matlab.

8. Title of the Project: Round Robin Scheduler for Rate based queues

Description: The 8 rate Q blocks with rollover as output indicate requests to

access the transmission channel. These requests are served by an arbiter in round

robin fashion.

Software Tools: Model Sim, ISE

9. Title of the Project: Automatic Station Announcement in Coaches

Description: To alert the passengers about the approaching station. The

approaching station name will be announced through audio device and displayed

on LCD

Software Tools: Keil Software

Hardware: RF Transmitter, RF Receiver, Micro controller, Voice chip

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