RESUME

ADAM KHAN Email: acgxy1@r.postjobfree.com

Male, Indian Mobile: +91-994*******

Objective:To work in an environment that would enable me to utilize my knowledge, commitment and

hard work and also provide an ambience to sharpen my skill sets in VLSI Domain.

Synopsis:

Master of Engineering from C R Reddy college, Andhra University, Eluru.

Ability in learning new concepts quickly, working well under pressure and communicating ideas

effectively.

Show initiative by taking on new and challenging tasks, and completing them on time.

Adeptness in handling multiple priorities, with a genuine interest in personal and professional

development.

Team player with ability to work independently& have strong analytical, leadership, interpersonal

skills as well as ability to work effectively in fast paced environment.

Technical Skills:

Good understanding of CMOS basics and its Fabrication process.

Strong foundation in Digital Design concepts.

Sound knowledge of Digital Circuits.

Proficient in C,Verilog.

Good Understanding, System Verilog.

Experience with RTL & Behavioral coding with Verilog.

Experience in writing test benches using Verilog.

Experience with synthesis and optimization of Verilog code.

Simulation tool experience with Mentor Graphics Questa sim, Xilinx ISE.

Experience with FPGA implementation with Xilinx.

Educational Qualifications:

Degree Institute Board/University Year Percentage

C R Reddy College, Andhra University 2014 8.5 Cgpa

M.Tech

Eluru Vizag.

(VLSI)

Akula Gopayya JNTUK, Kakinada. 2011 65.90%

B.Tech

College,Tadepaliudem

(ECE)

Smt.B.Seethe State Board Of technical 2008 71.47%

Diploma

Polytechnic College, Education and Traning,

(DECE)

Bhimavaram Hyderabad

Vidya Deep Board Of Secondary 2005 76.8%

S.S.C

School, Nidadavole Education, AP

Projects:

1.DESIGN AND IMPLEMENTATION OF APB BRIDGE BASED ON AMBA 4.0

Synopsis: The aim of this Project is to Design and BRIDGE to provide communication Between AXI4

and APB, As most of the peripherals don’t use the advanced features of AXI4 bus, the APB bus has

been implemented to interact with the processor to reduce complexity. The bridge provides an interface

between the high-performance AXI bus and low-power APB domain. It has a Slave interface which

receives the AXI4 master.

Tool: Questa sim-6.10b.

2.Design and Implementation of Digital Clock using Verilog HDL

Synopsis: This project involves in developing the Digital watch using multiple counters. I designed and

implemented complete functionality of digital clock in Verilog and checked for all corner case scenarios.

I gained experience in debugging for all possible error cases.

Tool:Questa sim-6.10b.

3. Design and Development of Configurable Arbiter

Synopsis: The purpose of this project is to design and develop configurable arbiter using Verilog HDL

where the number of requests can be configurable from 2 to 16. The project also involves developing the

configurable arbitration algorithm, such as highest priority or round robin.

Tool: Questa sim-6.10b

Achievements:

M.tech 3rd semester college 1st with 9.99 SGPA.

Efficiently Coordinated Workshop on Advanced Digital Design using Verilog HDL Organized by

Osmania University, Hyderabad Apr – 2014.

I Stood 1st in INTERNATION CONFERENCE ICAEM 2104 Held in ONGOLO RISE Eng

College.

Declaration:

I hereby declare that the information provided above is accurate to the best of my knowledge.

DATE:

PLACE: Hyderabad (ADAMKHAN)

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