RESUME

Viplav Kankapurkar,

S/o Anand Rao,

HNO.*-4-58/2,G3,Raghava Apts, Lingampally

Kacheguda, Barkatpura-500027 Email

Id:acgxwm@r.postjobfree.com

Mobile: 964-***-****

CAREER OBJECTIVE:

To work in pragmatic way in an organization where I can show my talent and enhance my skills

to meet company goals and objective with full integrity and zest and to excel in my field through

hard work, research, skills and perseverance.

ACADEMIC QUALIFICATIONS:

Qualification University Specialization Year of passing Marks in %

Electronics and 79.6

JNTU 2014

B.Tech communication

Engineering

Board of Mathematics,

Intermediate Intermediate 2010 91.1

Physics, Chemistry

Education

Board of

2008 83.6

SSC secondary school

education

TECHNICAL SKILLS:

Languages like ‘C’, Java Basics, ‘ASSEMBLY’ Language (MASM 611).

Software operation like MULTISIM, MATLAB.

Worked on platforms like Xilinx ISE.

Good understanding of the ASIC and FPGA design flow.

VLSI Domain Skills

HDLs: Verilog

HVLs: System Verilog, UVM Basics

EDA Tool: Xilinx ISE, Questasim

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Synthesis, Static Timing Analysis, Reusable Test Bench &

Verification Environment.

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

Year: August 2014

PROJECT INFORMATION AND INDUSTRIAL VISITS:

Under the guidance of Prof. Lathkar sir, I have done an IETE (INSTITUTE OF

ELECTRONICS AND TELECOMMUNICATION ENGINEERING) mini project on

‘TWO WAY INTERCOM’ and other projects like DRRM (DIGITAL RATE

RESPIRATION METER), smoke alarm, and laser intruder alarm.

Had been to ‘ICOMM’ and ‘HINDUSTAN BATTERY LIMITED’ (HBL) as a part of

industrial visit.

Also have done a project on ‘GPS based Vehicle Navigator’ under the guidance of Prof.

Vinay Patankar.

A Project on “Data acquisition system” at NRSC.

Router 1x3 – RTL design

HDL: Verilog HVL: UVM

EDA Tools: ISE

Description: The router accepts data packets on a single 8-bit port called data and routes

the packets to one of the three output channels, channel0, channel1 and channel2

Responsibilities:

Architected the design

Implemented the RTL using Verilog HDL

Verified the RTL using Verilog HDL & UVM

Generated code coverage and Functional coverage

Synthesized the design

POSITIONS OF RESPONSIBILITY:

Led a 16 member group in ‘Re-chording’ for community work.

An active member of IETE.

EXTRA AND CO-CURRICULAR ACTIVITIES:

Participated in 15th Geomap quiz (gems) at Hyderabad.

Participated in “SCIENCE FAIR ORGANISATION” at Brilliant grammar high school.

Participated in technical fest conducted at IIIT-H and CBIT.

STRENGTHS:

Discipline, hard work, honesty, decision making towards a task is one of my strongest

points. My confidence and command over my language is an addition to my strength.

My parents support is one of my biggest strengths.

I look at a matter with ease and soothe and try to accomplish it by giving my best.

PERSONAL DETAILS:

Name : Viplav Kankapurkar

Father’s Name : Anand Rao

16th November 1992

Date of birth :

Gender : Male

Hobbies : Soft music, Playing Guitar, basketball, cricket &

chess.

Nationality : Indian

Address : 3-4-58/2, G3, Raghava Apt, Barkatpura.

Languages known : English, Hindi, Telugu, Marathi & Kannada.

Personal traits : Optimistic, Skillful, Hard Working & Honest

DECLARATION:

I hereby solemnly declare that the above furnished details are true to the best of my knowledge

and shall be able to submit the documents if required, on demand.

Place: Bangalore (K.Viplav)

Date:

Contact this candidate