Ranjith Acharya

S/o Late Mohandas Acharya Email: acgthb@r.postjobfree.com

“Bhoo Varaha Nilaya”, 2055 Contact No.:741*******

East End ‘B’cross, 38th main

Jayanagar, Bangalore-560069

Objective

Eagerly waiting for an opportunity to work in an organization that will utilize and enhance my skill

set in the field of semiconductor industry.

Current Status

Finished VLSI Design Course in Full Custom Layout Design and Verification under VTU

Empower 10K Program (200 hrs training program) in MS Engineering Collage Research

Centre, Bangalore.

CMOS circuit Design

Layout Design

Academic Profile

B.E. in Electronic and Communication (2010-2014) from “Shri Madwa Vadiraja Institute of

Technology” Bantakal, Udupi.

Aggregate: 62.53%

12th Grade (2008-2010) from MGM PU Collage, Udupi.

Overall Percentage: 61.5%

10th Grade from Government High School Valakadu, Udupi.

Overall Percentage: 75.04%

Technical Exposure

• Basic knowledge of both analog and digital layouts.

• Proficient in drawing layouts of Differential amplifier, Operational Amplifier, basic ESD

circuit, Level Shifter, R2R DAC and many more.

• Basic knowledge of layout design issues.

• Familiar in resolving various timing (STA) issues in a chip.

• Proficient in HSPICE simulator tool.

Tools and Language detail

Hardware Description Language : Verilog and VHDL (Beginner)

EDA Tools : HSPICE

Software Skills : C, Perl (Beginner)

Layout Editor : Virtuoso (Cadence)

DRC/LVS Tools : Assura (Cadence), Calibre (Mentor Graphics)

Schematic Simulator Tools : Spectre(Cadence)

Eldo Simulator (Mentor Graphics)

Projects Undertaken

1. Project: “Design of 64 bit SRAM Memory Unit”

Tools used: HSPICE and CADENCE

Description: Aim of this project was to design a low power and high speed 64 bit SRAM cell in

180nm technology.

Role:

Responsible for designing bit cell, sense amplifier, decoder, control block and I/O drivers.

Responsible for designing efficient layout.

2. Project: “Design of a basic Mixed Signal I/O cell”

Tools used: CADENCE

Description: Aim of this project was to design proficient layouts for basic ESD protection circuit and

level shifter circuits.

B.E project

Project: “Design & Development of a GSM Based Vehicle Theft Control System.”

Tools used: Micro C and Kiel.

Description: Aim of this project is to prevent the theft of a vehicle and tracking the vehicle.

Industrial Training

Attended training at Advanced Electronic Systems (ALS), Bangalore of 1 week duration.

Core Electives in B.E.

CAD for VLSI

Satellite Communication

Personal Details

Marital Status : Single

Date of birth : 18-04-1993

Languages Known : English, Hindi, Kannada and Tulu.

Permanent Address : “Panchajanya”, V.M.Nagar, 11th cross

Doddangudde, Udupi.

Declaration

I hereby declare that above mentioned details are correct up to my knowledge and I bear the

responsibility for above mentioned particulars.

Ranjith Acharya

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