R. Scott Tetrick

503-***-****

Portland, OR ***29 acgsjs@r.postjobfree.com

SUMMARY

Leader delivering impactful, multifaceted solutions to effectively solve problems in hardware,

software, firmware, and silicon architecture. Dynamic professional who transforms unfocused

initiatives into actionable, definitive strategies. Recognized subject matter expert in platform

architecture across multiple segments including CPU, memory, and I/O. Prolific thought leader

with 50 patent applications approved / in process and 12 industry publications. Motivational

team builder, coach, and mentor.

Hardware Architecture and Development Project Management and Leadership

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Analytical Processing and Data Analysis Tool and Simulator Development

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Strategic and Competitive Planning Intellectual Property

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Python, C, C++, R with big data processing Innovative builder of methods to take data to

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and visualization drive broad decisions

PROFESSIONAL EXPERIENCE

INTEL CORPORATION, Hillsboro, OR 2000-2014

Global leader in semiconductor manufacturing

Principal Engineer, Mobile and Graphics Architecture, 2007-Present

Platform architect addressing memory and storage issues on phone, tablet and laptop products.

• Developed Python analysis tools for examination of disk accesses for developing insights in

patterns and methods used, allowing direct comparison of disks from different manufactures

to address system requirements for hardware and operating system. Used library packages in

Python for numpy, matplotlib, h5py, multiprocessing and R interface support to create

persuasive visualizations.

• Used Python to develop a detailed DRAM power model for graphics accesses. Required

interfacing with C-based simulation model to extract necessary information to determine

application-based values for power consumption. Used results to influence graphics memory

hierarchy to improve power efficiency.

• Developed Python simulation tools for new disk technologies. Modeled new interfaces and

materials, applying changes to existing storage traces to determine possible improvements

and limitations. Developed interactive visualization tools to examine parallelism

opportunities in Python.

• Led memory architecture requirements for graphics development, driving needed strategic

capabilities in platform segments from phones to workstations. Drove memory usage

requirements for capacity and bandwidth for graphics and media use. Used Python to create

tools to zoom into critical transaction behaviors to determine bottlenecks.

• Directed memory hierarchy and silicon changes delivering power and performance gains

with graphics workloads, improving performance up to 30% at constant power.

• Developed simulation tools and analysis techniques to demonstrate gains from new memory

technologies, and demonstrated by writing Android and IOS applications to show benefits.

R. Scott Tetrick 503-***-**** Page 2

• Drove analysis and changes of driver and operating system to reduce storage power

consumption by 20%. Successfully persuaded OSV partners to adapt algorithms to deliver

gains in all products.

• Delivered significant optimizations supporting new solid-state devices running current

operating systems. Reduced mobile SSD systems power consumption by 25% year over year

by addressing issues in SSD firmware, CPU power processing, and driver algorithms.

• Created Python-based tools and benchmarks to examine disk-caching methods for SSDs for

responsive behavior. Used visualization techniques to show storage accesses to promote

changes to driver development and strategic planning teams.

Principal Engineer, CPU Architecture, 2000-2007

Leader of cross platform CPU architecture team developing performance and power

opportunities by delivering changes in memory and silicon capabilities.

• Drove delivery of higher speed DRAM connections to CPU and chipset, providing 10%

performance enhancements. Implemented all changes in CPU performance simulator.

• Processed memory transactions with self-developed Python tools to examine performance

limitations in multiprocessing environments. Extracted performance analysis information

with code for examination of internal chipset counters. Limited counters required

development of methods to merge different runs together into a time-synchronized composite

for analysis.

• Led Platform Engineering Board activities that developed performance and power delivery

techniques for Pentium 4 processors, and provided information to OEMs to speed product

delivery of new CPU systems.

• Delivered front side bus improvements for multiprocessing systems. Resulted in 25% system

performance improvement on server database workload.

• Presented interface improvements for network solutions at ISCA 2005, implemented in Intel

server processors as IOT to support high speed networking requirements for minimum packet

processing latencies.

• Accomplished 10% performance improvement across desktop platform through modified

DRAM addressing. Developed analysis method using genetic algorithms with C-based

analysis of address traces. Partnered with Intel chipset DRAM controller team to deliver in

products.

• Addressed DRAM power changes due to multiprocessing and hyperthreading. Developed

detailed testing methodology to avoid issues, and authored corporate paper and training class

to inform technical community.

• Directed hardware architecture for digital home products. Evaluated multiprocessing /

virtualization solutions for consumer videos issues. Examined multiprocessing impacts to

platform including front side bus and memory bandwidths.

Held additional Positions as a Senior Engineer (High End Server Products at Intel); Senior

Engineer and Manager (Server Development at Sequent Computer Systems) and Engineer

(Multibus and PC Development, Intel Corporation).

R. Scott Tetrick 503-***-**** Page 2

EDUCATION

Post Graduate Studies (15 credit hours), Computer Science

Oregon Graduate Institute, Beaverton, OR

Bachelor of Science, Electrical Engineering and Computer Science

Massachusetts Institute of Technology, Cambridge, MA

ADDITIONAL RELEVANT INFORMATION

IEEE Member, Draft Editor of IEEE 1296 specification of Multibus II

Presented 12 industry publications and papers most recently at ISCA 2005

More than 50 patents granted / pending

Led private, non-profit organization

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