Sathish T N

Objective: An Enthusiastic and dynamic person looking for career

opportunity as VLSI front end Engineer in a part of organisation and to

work with passionate and association for growth and development of

organisation.

Chennai, India. Mail: acgs60@r.postjobfree.com Ph: (91-963*******

Work Experience

Project-Intern, Maven silicon soft tech, Bangalore July' 14

- till date

> Design & Functional verification of AHB-APB Bridge; Platform: Verilog;

Tools: Xilinx

. Description: The Bridge is used to interconnect between AHB and APB.

Bridge design has been done with single master and single slave.

Design modules consist of AHB slave and FSM controller acts as APB

master. Meanwhile AHB bus acts as master and APB bus acts as slave.

. AHB master generate the address using Increment and Wrap burst

logic.AHB to APB bridge functional verification is done in Verilog.

> Design &Functional verification of SPI; Platform: Verilog; Tools: Xilinx

. SPI Design is open core technology independent wishbone compatible

project. Module consists of slave clock generator, shift register,

slave module and wishbone module.

. Slave clock generator is used to generate the slave clock; Shift

register is used to shifts data between wishbone and SPI slave.

. Slave module is used to drive the master input (slave output) and

collect the master output (slave input).

> Verification of AHB to APB; Platform: System Verilog; Methodology: UVM

. AHB to APB Bridge RTL has been verified in UVM methodology. Test bench

acts as AHB master and APB slave as well.

. Test cases which are verified single write data, single read data,

write data from master to slave (addresses are generated using burst

operation), read data from slave to master.

> Verification of UART IP core; Platform: System Verilog; Methodology: UVM

. The UART core RTL is technology independent and fully synthesizable.

The UART IP core consists of a transmitter, a receiver, a modem

interface, a baud generator, an interrupt controller, and various

controllers and status registers.

. This core can operate in 8-bit data bus mode or in 32-bit bus mode. It

is an interface between wishbone and UART transceiver, which allows

communication with modem or other external devices, like another

computer using a serial cable and RS232 protocol.

. Verification: Two UART has been used to verify the core RTL. First

UART acts as a transmitter and other UART acts as receiver and vice

versa. Both are operating with different frequency but same BAUD rate.

Test cases like full duplex, half duplex and loop back modes has been

verified.

Component Engineer, KONE elevator and escalators, Chennai

Feb' 10 to July'13

. Key Area: In the supply operation of Finland which is the global

supply chain of KONE. Worked as a supply line co-ordinator designing

the required solution according to the specification that the front

Line (FL) has agreed with customers.

. Roles & Responsibility: Identify and select the components required

for designing the individual components meeting customer specific

requirements. Customized wiring diagrams and Bill of Material (BOM)

will be made for the special options/requirements of customer.

. Ensuring all the components used are comply with EN standards and Lift

directives to make the product suitable for European markets. Also the

local country codes and standards like SWISS regulations, PUBEL

(Russia) regulation also followed when needed.

. Providing the necessary solutions and interface for modernization

products which uses other manufacturer components.

. Estimate customer order packages and carrying out feasibility studies

to conceive electrical designs to meet specifications at optimal total

cost

. Achievement: Training and technical support has been provided to

Supply operation of China Electrical engineers.

Trainee Engineer, ACCEL FRONTLINE, Chennai Nov' 09

- Jan' 10

. Key Area: Have been worked as part of product unit, as a trainee

engineer training has been provided for testing the 1KVA to 10 KVA

UPS.

. Roles & Responsibility: Testing of various rated UPS and quality

assurance of electrical components like Batteries, coolers, various

rating of transformers etc which is used to install in UPS.

Technical skillset

Hardware Design Languages: Verilog HDL.

Hardware verification Language: System Verilog.

Test Bench Methodology: Universal Verification Methodology.

EDA Tools: Xilinx, Model SIM & Questa SIM.

Domain: ASIC/FPGA Design Flow, Digital Design

methodologies

Scripts: TCL, PERL

Others: RTL Coding, FSM based design,

Simulation,

Code Coverage,

Functional Coverage, Synthesis,

Static Timing Analysis, Assertion Based

Verification.

Certifications

> Certified as VLSI Design & Verification engineer in Maven silicon soft

tech Pvt. Ltd.

. Training Period

Aug' 13 - Dec'13

. Internship period Feb'14 -

Apr'14

Educational qualification

Bachelor of Engineering in Electrical and Electronics, Anna University,

2009; 72%

Higher Secondary, Govt Boys HS School, Thimiri, Vellore Dist. 2005; 76%

SSLC, Govt Boys Higher Sec School, Thimiri, Vellore Dist. 2003, 83%

Place: Chennai

Date: (Sathish T

N)

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