Tuheen Ojha

CELL 312-***-**** • E-MAIL acgrq8@r.postjobfree.com

**** ********* **** #** *** Jose, CA 95126

EDUCATION:

University Of Illinois(UIC)

Department of Electrical & Computer Engineering (M S) Graduation :May 2014 GPA:3.5

Bachelors of Technology (Vellore Institue of Technology)

Department of Electrical & Computer Engineering Graduation: May 2010 GPA: 8.0

LABORATORY SKILLS:

Simulation Tools Matlab, Cadence (Virtuoso), Xilinx ISE Design Suite

13.4,Vivado2013.4,Altera,Quartus,Modelsim,Atalanta test vector

generator(ATPG),Aldec-StudentEdition,Adept2,Questasim,Synopsys VCS

Simulator,IAR simulator(ARM Cortex M4),Pspice,Hspice

Specialized Logic Analyzers, Function Generators, Oscilloscopes (Agilent/Tektronix),

Laboratory Spectres, Digital Communications Analyzer

Experience

Programming C, C++, Python,Perl,Assembly level programming in 8086,

Languages 8051,makefile,Verilog,Systemverilog,CUDA-C++

Operating Platforms MS Windows, Mac, Linux (Redhat and Ubuntu)

Design &Verification Skills:

Design: Verilog Constructs, FSM, Synthesizable RTL, and Design Assertions.

•Verification: Functional Verification, Test Bench development, Scripting, Regression, Code

Coverage.SystemVerilog, UVM, OOP, Constrained Random Verification, and Assertions,

TLM port.

Academic PROJECTS:

FPGA and Verilog Projects

• Keyboard and Mouse controller to FPGA Spartan 3E(device to host communication) :Designed

Keyboard and mouse interface to PS/2 port of Spartan3E in verilog using Xilinx (13.4). State diagram

of a keyboard controller stores the key scan codes(make,break codes) in a 11 bit shift register and

state flow is controlled by data clock of the device. The received data port of the PS/2 controller is

connected to the two HEX displays through a decoder, so that you can see the hexadecimal 8 bit value

of the code.

• FPGA as Video generators: PONG game: The pong game consists of a ball bouncing on a screen. A

paddle (controlled from a mouse ) enables the user to make the ball bounce back up. Verilog is the

language used and device FPGA Spartan 3E family.

• Designed Block ROM Memory component for Greatest common divisor and An Integer Square

Root Algorithm in FPGA using core generator: Upper nibble and lower nibble coming from the

block ram is passed into the GCD(greatest common divisor) component to produce the output

displayed in 7 Segment LED display unit. Control unit is designed that provides all the timing

information in the form of Moore state machine. Control unit and data path is finally combined to

complete Integer square root and GCD algorithm.

• Screen Saver using Verilog and FPGA: Bounce algorithm is implemented by designing a bounce

module with a use of 190hz clock module to make the image go from top of the screen to bottom of

the screen in 1.7 secs.

• Designed 8 bit custom made RISC Processor using Verilog in FPGA.

Layout(Backend) Design projects:

• Design of 5-stage Voltage Controlled Ring Oscillator with CMOS in 180nm process.

Tuheen Ojha

CELL 312-***-**** • E-MAIL acgrq8@r.postjobfree.com

2050 Southwest Expy #82 San Jose, CA 95126

• Low Power CMOS Voltage Mode SRAM Cell for High Speed VLSI design: Design is modeled

using Cadence simulator in 90nm and power dissipation of SRAM cell is calculated at different

operating frequencies.

GP-GPU Programming

• Learned the GPU programming model and architecture, key algorithms and parallel programming

patterns, and optimization techniques.Using cudaC++ fast conversion of colored image to grey image

was performed using parallel computation.Performed analysis on matrix transpose using threads per

row, threads per column, coalesced memory accesses using tiling.

• Performance Analysis on SuperScalar Processor and Cache Replacement Policy Performance of

super scalar processors was compared with simple pipelined processors and by using SPEC2000

benchmark program, equake various performance impacting parameters like branch predictors,

importance of speculative execution were further analyzed and conclusions were made.

• Evaluating Integrated graphics Processors for data Centre Workloads: Performance of integrated

GPUs are being evaluated and results reveals many architectural caveats that programmers need to

be aware of to exploit integrated GPUs: memory contention between CPUs and GPUs ;workload

dependent energy efficiency and data transfer tradeoffs.

• GPIO Access Through IAR workspace

ARM Cortex M4 (LM4F120 Stellaris LaunchPad): Studied the architecture of the TI LM4F120 ARM

cortex M4 Controller with special regard to GPIO addressing.

• Test Volume reduction for system on Chip testing using ATE(DFT) : Using Redundant vector

Algorithm in Perl, Extended Run length Algorithm performed Compaction and Compression of test

vectors which were applied on Scan chan by stitching technique helps in reduced memory storage

and speeding up the test time of on chip testing .

INDUSTRIAL EXPERIENCE:

ASIC Verification Intern and Trainee at VERIFAST TECHNOLOGIES(San Jose, CA)

• Uart Recevier Module Verification: Developed Testplan and verification architecture to collect

features or scenarios to be verified. Verified Uart serial to parallel RTL using System Verilog and

then converted the same testbench to UVM environment and reported the functional coverage for

the same.

• File based self checking testbench :Integrated all functional RTL modules and created a system

level top. Perl scripts where written to manage the files and test cases.

• Router DUT verification: Built Verification Environment to meet the Black Box Router DUT

specification by development of driver class, Receiver class, scoreboard, coverage class and

Tuheen Ojha

CELL 312-***-**** • E-MAIL acgrq8@r.postjobfree.com

2050 Southwest Expy #82 San Jose, CA 95126

packet class based on the stimulus plan. Used Constraint random verification was used along with

weights to cover various test scenarios and execute the corner cases in System Verilog.

• UVM Based Verfication Project:Developed a conventional test bench to verify tinyALU

design.Converted the conventional testbench to UVM testbench, verified the design and reported

the functional coverage of the UVM testbench.

• Worked on the Peripheral Interface for Amba APB Bus Functional Model (BFM).

• Amba Apb bridge controller Interface verification: Testbench build in UVM, apb transaction

were driven to the slave interface and the monitor being able to see the interface toggling and

reporting out those as transactions.

Contact this candidate