DINESH VARMA PENUMETCHA

Email acgo63@r.postjobfree.com Mobile No : 937-***-****

www.linkedin.com/in/dineshvarma/

OBJECTIVE

To work in an innovative environment with a high propensity towards

learning and where I can employ my designing and debugging skills

EMPLOYMENT

Intern July 2014 - Aug 2014

Oculii Dayton, OHIO

. Implemented a 8 channel simultaneous sampling ADC on TI F28377D micro

controller board in C++

. Assisted in Field testing of VISDAR device

Graduate Assistant Jan 2014 - present

International Collaboration and Graduate Programs at Wright State

University Dayton, OHIO

. Advised 50 graduate students

. Implemented a systematic method to students for course registration

Junior Design Engineer Apr 2012 - Jun 2013

Next generation Systems and Solutions(NSS)Communications Hyderabad, India

. Designed and Tested IP cores on VHDL and MATALAB platforms

. Wrote Scripts in C to generated VHDL codes based on requirements

selected in GUI

. Equivalent Simulink models of PLL, TED Designs

EDUCATION

Masters of Science in Electrical Engineering Aug 2013- Present

Wright State University(WSU) Dayton, OHIO

. GPA-3.73/4.0

Bachelors of Technology in Electronics and Communication Engineering

Oct 2008 -Apr 2012

V.R.Siddhartha Engineering College Vijayawada, India

. GPA-3.83/4.0

SKILLS, TOOLS and HARDWARE's

. Hardware: PMODAD1, FPGA Boards(Spartan3, Spartan 3E, Spartan6, Virtex

6), TI Micro controller boards

. Programming languages: C, VHDL, MATLAB, Python, Lab VIEW, SIMULINK

. Tools: Modelsim, Xilinx ISE, Quartus II, Cadence(SimVision, Virtuoso,

Encounter), TetraMax, CCS, MS Office

ACADEMIC PROJECTS

12 bit Asynchronous Multiplier using NULL Conventional Logic (NCL)

Designed a 12 bit dual rail logic asynchronous multiplier with threshold

logic gates using top to bottom hierarchical model. Simulated, Synthesized

(Technology map, placement, and route) and implemented the design on Xilinx

Virtex6 FPGA board and observed the synthesized results using ChipScope.

Dual Redundant bit checker

Designed a two 32bit sequence detector in VHDL with least states and

Synthesized(Physical synthesis) the design all the way down to layout using

cadence RTL compiler and Encounter tools and simulated the net lists of

synthesis and PAR to verify timing constraints and least Power Delay

Area(PDA) product was achieved.

ATPG for a 56-Bit Timing-Driven-Testable Convergent Tree Adder (TDTCTA)

Designed, simulated and tested 56 bit carry look ahead adder which were

written in verilog and VHDL hardware description languages. Using stuck at

fault model determined total number of faults, generated test patterns

using Tetramax and achieved 100% fault coverage. Compared 56b TDTCTA with

56 bit Testable convergent tree adder (TCTA) results and observed the

fanout effects in TCTA which has more delay or latency compared to TDTCTA.

8 bit RISC Y CPU

Implemented 32 bit instruction set architecture using top down hierarchy

model and simulated the synthesizable VHDL code.

Implemented the blocks of architecture like the scalable MUX, 8 bit

register, 5 bit synchronous counter, Scalable RAM, 8 bit ALU, Sequence

controller and phase generator in VHDL with one master clock and

asynchronous reset. Observed and learned how the instruction flows in

different stages like Fetch, Decode, Fetch operands from memory, Execute

and storing the result.

Contact this candidate