* ***** ** ********** ** Validation and Verification Engineer at Synopsys

India Pvt Ltd, Hyderabad and undergone 6 months of training in VLSI System

Design at CDAC Mumbai and certified with placement in Grade A

Objective

To be associated with a renowned and dynamic organization where I can use

my technical expertise and Team lead skills to deliver innovative solutions

and bring growth and success for the company and myself.

Summary

> 2 Years of experience in analyzing, designing, verifying and debugging

of test cases on Universal Verification Methodology, System Verilog,

System Verilog Assertion &Verilog.

> Undergone training on Universal Verification Methodology

> Good understanding of AMBA Protocols.

> Thoroughly involved in Unit testing for the many new features in

System Verilog LRM.

> Documentation: Test reports, Test Plans and writing Test Procedures.

Academic Qualification

Master of Technology from Vaagdevi College of Engineering Warangal, JNTUH,

India

VLSI SYSTEM Design, secured 70.5%, (VCE Warangal, JNTUH, 2012)

Bachelor of Engineering from S.R Engineering College Warangal, JNTUH, India

Electronics and Communication, secured 64.04%, (SREC Warangal, JNTUH, 2009)

Board of Intermediate from Kakathiya Junior College, Narsampet, India

Physics, Chemistry, Mathematics & Electronics, secured 88.7%, (KJC,

Narsampet, 2005)

Proficiency of Skills

Hardware Description Language: VHDL, Verilog.

Hardware Verification Language: System Verilog.

Verification Methodology: Coverage Driven Verification, Constrained Random

Verification.

TB Methodology: Universal Verification Methodology.

EDA Tools: VCS, Modelsim 6.3, Xilinx ISE, Micro wind.

Knowledge: Functional Coverage, Code Coverage, Simulation, FSM based

design, RTL coding, Basics of Perl and Tcl scripting, Simulation,

Synthesis, Digital Design Concepts, PCB Designing, ASIC (Basics).

Knowledge of ASIC Flow: Design-RTL Design, RTL Verification, Synthesis, PCB

Designing software and hardware, layout and schematics, timing constraints,

FPGA, CPLD, CMOS VLSI Designs.

Project Summary

Project 1: I2C BUS MASTER IMPLEMENTATION

Organization: CDAC, Mumbai.

EDA Tools: ModelSim, Xilinx.

Languages: Verilog, SystemVerilog.

Project Duration: 6 months

Members Involved: 4

Description: I2C is a two-wire, bi-directional serial bus that provides a

simple and efficient method of data exchange between devices. It is most

suitable for applications requiring occasional communication over a short

distance between many devices. The I2C standard is a true multi-master bus

including collision detection and arbitration that prevents data

Corruption if two or more masters attempt to control the bus

simultaneously.

The interface defines 3 transmission speeds:

- Normal: 100Kbps

- Fast: 400Kbps

- High speed: 3.5Mbps

Only 100Kbps and 400Kbps modes are supported directly. For High speed

special IOs

are needed. If these IOs are available and used, then High speed is also

supported

Role:

1. Study of user manual and functional features of the I2C protocol.

Involved in understanding and discussion on the functional spec of

I2C protocol.

2. Architected the class based verification environment using System

Verilog.

3. Generated functional and code coverage for the RTL verification.

Project 2: DESIGNING AND CONTROLLING ELEVATOR USING A STEPPER MOTOR

Organization: CDAC, Mumbai.

EDA Tools: Xilinx.

Languages: Verilog.

Project Duration: 1 month

Members Involved: 2

Role:

1. Assertion plan was created for the design.

2. Properties were written for the plan and formal verification was

done using Xilinx.

Project 3: Validation of Assertion and Coverage related switch feature in

System Verilog LRM3.0v.

Organization: Synopsys India Pvt Ltd, Hyderabad

EDA Tools: VCS.

Languages: Verilog, System Verilog.

Description: Validation of assert hier, cm assert, cm cond, cm_hier and

cm_assert_hier switch feature in System Verilog LRM3.0v.

Project Duration: 6 months

Members Involved: 2

Roles:

1. Carried out unit testing for above switches and validated in

existing testcases.

2. Involved in coding using Verilog, System Verilog, SVA and UVM.

Project 4: Validation of Pre-compile IP flow & Partition Compile auto-

partition of modules and packages

Organization: Synopsys India Pvt Ltd, Hyderabad

EDA Tools: VCS

Languages: Verilog, System Verilog and UVM.

Description: Ability to pre-compile self contained portions of design

and/or verification units into Pre-Compiled IP libraries i.e. Compiling

only that part of IP in SOC, that was modified and thereby reducing the

recompile time of the entire design. Ability to create partitioning based

on file size & threshold limit for modules and packages, carried out unit

testing and validated in existing test cases.

Project Duration: 6 months

Members Involved: 1

Roles:

1. Carried out unit testing for above switches and validated in existing

testcases.

2. Involved in coding using Verilog, System Verilog, SVA and UVM.

Academic Project during M.Tech

Title: Implementation of Linear and Four Morphological operators for Image

Filtering on FPGA

Work: Field Programmable Gate Array (FPGA) technology has become a viable

target for the implementation of real time algorithms suited to video image

processing applications. The

Unique architecture of the FPGA has allowed the technology to be used in

many applications encompassing all aspects of video image processing. Among

those algorithms, linear filtering

based on a 2D convolution, and non-linear 2D morphological filters,

represent a basic set of image operations for a number of applications. In

this work, an implementation of linear and

Morphological image filtering using a FPGA NexysII, Xilinx, Spartan 3E,

with educational purposes, is presented. The system is connected to a USB

port of a personal computer, which in that way form a powerful and low-cost

design station. The FPGA-based system is accessed through a Matlab

graphical user interface, which handles the communication setup. A

comparison between results obtained from MATLAB simulations and the

described FPGA-based implementation is presented.

Project Duration: 6 months

Members Involved: 1

Tools: Matlab, Xilinx, FPGA SPARTAN 3.E.DKT

Trainings Undergone

1. Advanced PG Diploma in VLSI training for 6 months from CDAC - Mumbai

2. Participated in Embedded Real Time Operating System Workshop for 2

weeks held at

Jayamuki College Of Engineering Narsampet, Warangal

Individual Potential

. Introspective to learn from mistakes, Responsible and optimist listener.

. Self motivated to Work well independently as well as part of a team.

Personal Details

Name :

Vikas Konkimalla

Father Name :

Sammaiah

Date of Birth :

26.05.1988

Nationality :

Indian

Marital Status :

Married

Languages Known :

English,Telugu,Hindi

Address :

Flat No:28 Sri Sai Nilayam, Near SBH ATM

Vivekananda Nagar, Borabanda, Hyderabad

Pin:500018.

Declaration

2

I hereby declare that the above furnished information is true to

the best of my knowledge.

Place: Hyderabad.

Your's Sincerely

Date:

[Vikas K]

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