BHAGHATH P J

email id:acgk9m@r.postjobfree.com Mobile: 812-***-****

948-***-****

Objective:

To pursue and excel in a professional career, with the best technical foundation, in order to explore newer

and challenging technologies with sincerity, hard work and determination.

Educational Qualification:

Course Institution University Percentage Year of

/CGPA Passing

M. Tech in VLSI-Very Amrita School of Amrita Vishwa

Large Scale Engineering,Coimbatore Vidyapeetham 7.79 2014

Integration Design

B. Tech in Electronics Sarabhai Institute of Cochin University

and Communication Science and Technology, of Science and 73.55% 2011

Vellanad Technology

Diploma in Govt.Polytechnic Board of Technical

Electronics College, Angadippuram Education, Kerala 81.36% 2007

VHSE in Vocational Higher State Board of

Computer Science Secondary Vocational Higher 71.52% 2004

School,Shornur Secondary

THS in Department of

2 wheeler and 3 Technical High School, Technical 62% 2002

Wheeler Repair and Shornur Education, Kerala

Maintenance

Projects:

M. Tech: SSTA using parallel processing of timing graphs

Timing analysis plays a vital role in chip design, which analyses whether a chip design meets the

timing constraints. The main objectives of timing analysis are speed and accuracy. There are two

engines for timing analysis namely Static timing analysis (STA) and Statistical Static Timing

Analysis (SSTA). VLSI CAD has been gaining a lot of interest in both STA and SSTA. As the

device size shrinks, tight control over process parameters is increasingly difficult. To account

these process parameters which are probabilistic in nature while performing timing analysis

SSTA is preferred. The main goal of SSTA is to improve the accuracy without any reduction in

speed by considering process variations. Earlier method for interpreting a timing graph as an

algebraic expression was based on addition and maximum operator. Due to reconvergent paths

there is reduction in accuracy and decrease in speed .The error due to linear approximation of

MAX operator which is used in PERT analysis is more. To overcome this, SSTA uses

Refactoring technique. This technique defines division operation on the expression and proposes

algorithms that modify factors in the expression without expansion. Novelty of this work

involves increase in speed of calculation of arrival time. SSTA incorporates parallel processing

with the help of CUDA programing model to reduce runtime. For the usage of CUDA

programing model it needs NVIDIA GPU because CUDA is supported only by the same.

TOOLS USED

• C compiler, CUDA, Synopsys Design Vision

OUTCOMES:

• Engine for PERT analysis to find number of literals using c compiler

• Engine for refactoring technique using c compiler which have higher accuracy when compared to

PERT analysis

• Engine for refactoring technique using CUDA programming model with achievement of 2X

increase (approximately) in speed without reduction in accuracy.

B. Tech:

Main Project: Dynamic Speed Governor using Sign Board Adaptive System

The project was to develop Dynamic Speed Governors in vehicles that will automatically control

vehicle speed as mandated by road sign boards. Apart from controlling speed, the system can

also be used to enforce ‘NO HORN’ regions (Hospital areas etc); no Parking zones, usage of

headlight dimmer at night.

Mini Project: Automatic lighting and security system for godowns.

In this project,an automatic lighting system is developedin which light in a godown is made

ON/OFF by detecting the presence of a person in thegodown with the help of a RF transceiver

and also an efficient security system is developed which uses a new device called I-BUTTON.

Diploma:Verilog Hardware Description Language

In this project, a CPLD IC was burned using CPLD trainer kit with the help of Verilog HDL

language.

Technical Skills:

General purpose languages : C& C++

Assembly Languages : PIC programing,8051, 8086,ARM

:

Design Languages Verilog HDL, Matlab

Parallel Programing : CUDA

Synopsys Tool : Hspice, Design Vision, Prime Time,

IC compiler,Star Extract,VCS

Layout Tool : Magic

Core Competency:

Strong logic and circuit design skills in Digital electronics.

Good verbal and written communication skills.

Very good analytical and debugging skills.

Publications:

1. Bhaghath P J and Ramesh S R. Article: A Survey of SSTA Techniques with Focus on

Accuracy and Speed. International Journal of Computer Applications 89(7):21-25,

March 2014. Published by Foundation of Computer Science, New York, USA.

This paper presents a survey of SSTA approaches and techniques for improving

accuracy and speed by considering topological correlation and spatial correlation.

2. Bhaghath.P.J, Ramesh.S.R,"A Comparison on Timing Analysis UsingProbabilistic Approaches",

Proceedings of the IEEE InternationalConference on Communication and Signal Processing.,

pp.419-423, April2014- Organized by Adhiparasakthi Engineering College, Melmaruvathur

This paper compares the arrival time, execution time of each deterministic timing

analysis, STA and SSTA. It states that accuracy is more for SSTA when compared to STA

and deterministic timing analysis with trade off in execution time

Personal Details:

Date of Birth : 30-05-1987

Contact Address : Vappalakalathil (h),Puthussery,Choondal (PO),Thrissur dt,

Kerala 680502

Languages Known : English, Malayalam

Hobbies : Travelling, Sports(Cricket, Carrom)

Declaration:

I hereby declare that the above mentioned details are true to best of my knowledge and belief.

BHAGHATH P J

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