RESUME

Mihir H. Parekh

D-**, King’s Park Society, Mobile No: 089******** / 738-***-****

***, ******* ******, **** ***********. Email: acgif3@r.postjobfree.com

OBJECTIVE

Strong desire to build my career and explore my current technical skills & knowledge in VLSI

design field.

CURRENY EMPLOYMENT DETAILS

Currently employed as Hardware Design Engineer in Mitsubishi Electric India Pvt. Ltd. in R&D

department at Pune, Maharashtra.

Having experience of less than 4 months.

EDUCATION PROFILE

Percentage

Course/Degree Year Institute / University

/ CGPA

M.Tech (VLSI Design) 2014 9.18 CGPA VIT Vellore (VIT university)

V.V.P. Engineering College, Rajkot

B.E. (E&C) 2011 76.54%

(Saurashtra University, Gujarat)

Saint Mary’s School, Rajkot (G.S.H.S.E.B)

H.S.C. 2007 79.00%

.

Saint Mary’s School, Rajkot (G.S.H.S.E.B)

S.S.C. 2005 81.29%

.

TECHNICAL SKILLS

Hands On Experience

Software Tools Programming Languages

Cadence – NC Launch, RTL Complier C, C++

Cadence – SoC Encounter (Back-end) Verilog

Mentor Graphic- Model-Sim PERL

Altera Quartus – II TCL

Cadence – Virtuoso W orked on – 45nm, 90nm & 180nm Nodes

Matlab

PROJECT DETAILS

1) Master Thesis on “Development of Power Estimator Tool (EDA)”

Duration: 1 Year

Summary:

The project describes the technique of estimating the dynamic as well as the static power

consumed by the digital circuit. This technique uses various design constraint files as its input

such as gate-level netlist, library file, VCD file and produces the power report. This method

uses “gpdk 180nm” library file for estimating the power.

Application: To determine the post synthesis power consumed by the digital circuit.

Tools used: CADENCE RTL Compiler, CADENCE NC-Launch, Turbo C++, Linux OS for

PERL Coding.

2) ASIC Design and Implementation of “Pipelined Division Architecture”

Duration: 6 Months

Summary:

Pipelining is a technique of splitting a sequential process into sub -operations with each sub-

operation being executed in a dedicated segment that operates concurrently with all other

segments.

This project proposes the design of “unsigned division opera tion” which is pipelined in order to

increase the clock frequency and reduce the clock period required to complete the operation.

Applications: ALU, FPU, Micro-controller Instructions, etc.

Tools used: MODELSIM, CADENCE NC-Launch, CADENCE RTL Compiler (Front-End),

CADENCE SoC-Encounter (Back-End), Language – Verilog, Technology Node – 45nm.

3) ASIC Design and Implementation of “All Digital Phase Locked Loop (ADPLL)”

Duration: 6 Months

Summary:

In Electronic design automation, clock generation is a basic need to synchronize user specific

design. Clock generation can be done using PLL.

ADPLL is modified form of PLL which contains digital blocks only and tracks the signal

frequency. It is used to lock the phase and frequency of a digital signal.

Applications: FSK Demodulator, clock generation, Removal of Clock Skew.

Tools used: CADENCE NC -Launch, CADENCE RTL Compiler (Front-End), CADENCE

SoC-Encounter (Backend), Language – Verilog, Technology Node – 90 nm.

4) ASIC Design and Implementation of “MCM Operation of FIR Filter”

Duration: 6 Months

Summary:

This project mainly focuses on the design of “Multiple Constant Multiplication” (MCM)

operation of FIR filter using the "shift-Add" architecture. In order to reduce the total number of

addition and shift operations, two algorithms known as Common Sub -expression Elimination

(CSE) algorithm and Graph Based (GB) algorithm are described for bit -serial and bit-parallel

architectures.

Applications: To build high speed FIR Filters.

Tools used: CADENCE NC -Launch, CADENCE RTL Compiler (Front-End), CADENCE

SoC-Encounter (Backend), Language – Verilog, Technology Node – 45nm, 90nm.

5) Verilog Design and Implementation of “ AMBA AHB to APB Bridge”

Duration: 6 Months

Summary:

In the System on Chip (SoC) design, a high performance data transfer is required between

different IP cores.

This project proposes the design of bridge between Advanced Microcontroller Bus

Architecture (AMBA) AHB and APB Buses. The bridge supports 32 and 64 bit peripherals

over a 64 bit AHB bus and 3 bit APB bus.

This bridge transfers the data of Masters connected to AHB bus to slaves connected with

APB Bus.

Tools used: MODELSIM, ALTERA-QUARTUS II, Language – Verilog.

6) 2D Object and Shape Detection Using MATLAB

Duration: 1 Year

Summary:

To detect and identify 2-D objects were implemented.

Algorithms for Circle detection, Character Recognition and Object Counting were proposed

and implemented.

Tool used: MATLAB

ACHIEVEMENTS

nd

2 RANK in University Final Year Exam, awarded Scholarship from V.V.P Engineering College

Qualified GATE-2012 held by IIT Delhi with 98.68 Percentile.

PUBLICATIONS, SEMINARS & PRESENTATIONS

Published master thesis project in “International Journal of Engineering Research and

Technology (IJERT)” in April-2014, volume-3, Issue-4, ISSN 2278-0181.

Presented a paper entitled “2-D Object and Shape Detection using Image Processing” in the

“International Conference on Innovative Science and Engineering Technol ogy (ICISET)” held at

V.V.P. College Rajkot Gujarat.

PERSONAL INFORMATION

Father’s name: Himanshu Bipinchandra Parekh

th

Date of Birth: 19 March, 1989

Languages Known: English, Hindi, Gujarati

Hobbies: Sports, Dance and Travelling

Gender: Male

Nationality: Indian

Marital Status: Single

Permanent Address: B-103, Maharaja Residency, New C.G.Road, Chandkheda,

Ahmedabad, Gujarat-382424

D/01 King’s Park Society, 151 Morwadi, Pimpri, Pune, Maharashtra.

Current Address:

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Pune

th

Date: 24 Sep 2014

Mihir H. Parekh

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