NEERAJ KUMAR GOYAL

E-mail: n eerajgoya acghdy@r.postjobfree.com Phone: +91-725*******

Job Objective

To seek job as a Physica l Design Engin eer so that I can use my technica l knowledge, experience & skills in th is field to

effectively con tribute to successful and p ro fitable operation of th e co mpan y.

Educational Details

Y ea r Board/Ex amination School/University Mark s

2008-12 B.E.(ECE) PEC University o f Technology, Chandigarh 8.21/10

2007-08 Class XII (CBSE) S.G.G.S Co llegiate Pub lic School, Chandigarh 86.00%

2005-06 Class X (PSEB) S.V.M High Scho ol, Dhura-Dhu ri 89.54%

Technical Sk ills

Design Tools: Ma gma - Ta lus, Caden ce- ETS, K2 Viewer, Apache- Redha wk, Xilinx IS E Design Suite 12.3

TI Internal Tools- Warpco re, Phoenix, Picasso

Programming and scripting Language s: Tcl, Perl, VHDL, C

Profe ssional Expe rience

Physical Design Engineer a t Texas Instruments,Bangalore July '12 – Aug '14

Worked in SOC Physica l Design Teams, responsib le fo r th e activities in the following p ro jects:

1. TI – ADAS-LOW SOC - 28 nm Proce ss April ’14 – June '14

Design targeted fo r Advance Driver Safety System in au tomobiles.

S igna l EM and Cell EM analysis/fixes.

PKG DRC ch ecks and metal DRC fixing

Resistance ca lculation u sing REDHAWK for non-bu ffered nets.

GDSII gen eration - PG'ed "go-for fab rica tion "

2. TI - J6ECO SOC - 28nm Proce ss April '13 - March '14

Design is targeted for Aud io & Infotainment System Applica tion s usage scena rios p rimarily in Auto motive Sectors. My

respon sibilities includes: IO Ring crea tion, Cu stom routin g, Backend checks. and Cross-domain Interactions with RTL

team to get the issues fixed du ring IO ring crea tion and custo m rou ting.

IO Ring Creation/ Bump-Map

o Complete own ersh ip o f IO Ring creation and Periph eral Bump Map

o Completed Bump to IO pad Routing and IO ring DRC cleanup

Custom Routin g & placement o f Analog IPs and Bumps

o Proposed and Imp lemented Bump Placement for power pins & cu stom routes for the integration of

Analog IPs in SOC to achieve resistance requiremen t from power bump to p in o f IP

DD R skew match rou ting and S ign Off

o Completed D DR signals skew ma tch routing and signed o ff th e skews using Cad ence ETS

o Custom routing wa s requ ired for matching signal delays for the rou tes between PHY and IO

ES D Placement a nd routing

o Decided the ESD clamp p la cement fo r the po wer pins o f analog IPs during floorplanning.

o Done po wer routes for IP Pin s follo wed b y ESD Strike checks.

Resistance checks for Custom Routes

o Signed o ff resistance values for custom rou tes for meetin g sp ec requirements o f IP and signals

Backend Checks

o Signal EM, Cell EM and Power EM analysis

Own ed flow setup, p reparing inputs, debugging and fixing issues.

o An tenna Check

Complete own ersh ip for flow setup and debugging and fixing o f An tenna Erro rs

o DRC Checks

Assisted in p erfo rming DRC checks & fixed metal DRCs for the complete d esign

Knowled ge o f c28 Ru le d eck

3. TI - J5ECO SOC TAPE OUT 2.0 -45nm Process April ’13 – June ’13

J5-Eco is a high performan ce mu ltimedia applica tion p ro cessor p la tform which targets for Automo tive D igital Ra dio

& Na viga tion applica tion s with video in put & camera input as backup a ssist.

Backend Checks

o LAFF build fo r Tape Ou t, DRC checks/fixing

Performed comp lete D RC ch eck of the d esign and fixed erro rs manua lly in the layout since top

level S TA rou tes were no t to be touched.

o Performed Antenna Ch eck fo r the design

o Assisted in LVS (Layout V s Schematic) setup and debug fo r the design closure.

Crea tion o f Knight Data for fou ndry d ebug.

4. TI - Vayu SOC - 28nm Process Dec ‘12 - Fe b ‘13

Design is targeted fo r DS P Ca ta log, Automo tive Infotain ment (D RI) & sa fety app lications for Automotive V ision.

DRC clean up for PIPEs

o Cleaned up the Meta l DRCs for the PIPEs in the design to help the tea m a ch ieve the Tap e Out in time

5. TI -OMAP6 SOC (TSV Technology) - Mobile Processor, 28nm Process Aug '12 - Nov '12

Design is targeted to a ch ieve mobile processing at a fa ster pace using TSV techno lo gy.

Performed D etour Nets Analysis in fix-cell DB and a ssisted the P& R team with critical movemen ts o f IPs in fix-cell

sta ge

Analysis of rou ting channels for congestion

o Scrip ted fo r Channel Estimation in TCL to id entify and h ighlight critica l channels in the layou t itself.

Design Intern at Bit Mapper Inte gration Technologie s, Pun e Jan '11 – June '11

1. Hardware Design and VHDL coding of FPGA based Gum Dispensing Machine Controlle r

Complete responsibility of the project ranging from ha rd ware design, coding, writin g so ftware fo r contro ller

using VHDL to final testin g and timely d elivery.

2. F unctional Testing of boards

Performed complete functional testin g of In terfaces like ADC,DAC,USB,SRAM,FLASH etc of n ewly fabrica ted FPGA

based boards, d ebu gging and fixing the issu es.

Re fe rence s: Available upon request

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