Adilakshmi Siliveru

Email id: acgfmz@r.postjobfree.com

Mobile Number: 998-***-****

Career Objective:

To achieve high career growth through continuous learning process and keep myself dynamic, visionary

and competitive with the changing scenario of technology.

Core Competency:

• Good knowledge of Digital Design Concepts.

• Good knowledge of CMOS concepts.

• Good knowledge of Full Custom flow & ASIC flow.

• Good exposure to technology by undergoing additional training in VLSI.

• Excellent understanding of SPICE Net list.

• Familiar with EDA tools like IC-Studio, PYXIS & CALIBRE.

• Excellent working experience of designing standard cells by using 180nm technology.

• Excellent working experience of designing 7 track 28nm and 9 track 90nm standard cells.

• Excellent knowledge of floor planning by maintaining proper source and drain sharing for area

optimization.

• Excellent working experience at Physical design verification like DRC, LVS and Compatibility

check.

• Good working experience of Analog Layout Design.

• Good working experience of Memory Layout Design.

• Good knowledge of DFM requirements.

• Basic knowledge in Verilog.

• Good working knowledge of Linux/Unix.

Education :

Institute Year of

Degree Discipline Aggregate

University Passing

PG

VLSI RV-VLSI Design Center 2014 Pursuing

Diploma

Sree Vidyanikethan Engineering

Electronics &

ME/M.tech College 2013 83 %

Communication

JNTU

Kandula Obula Reddy Memorial

Electronics &

BE/B.Tech College of Engineering (KORMC) 2011 63 %

Communication

JNTU

12th M.P.C N.R.Junior College 2007 88.8 %

Board Of Intermediate

10th ZP GIRLS HIGH SCHOOL 2005 80 %

Academic Projects:

Title: Design of Parallel Prefix Adders Based on Degenerate Pass Transistor Logic

Role: Design of Parallel Prefix adders using SPICE code

Organization: Sree Vidyanikethan Engineering college

Duration of Project in

Months: 8

Description: This project describes the low-power, Low-Complexity full adder design based

on Degenerate Pass Transistor Logic. The design is logically degenerate 5-

transistor XOR-XNOR module supporting complementary outputs. The

threshold loss problem is common in most Pass Transistor Logic designs can be

alleviated due to the availability of complementary control signals. In this

project, Kogge-Stone, Brent-Kung, Ladner-Fischer and Beaumont-Smith parallel

prefix adders are designed based on degenerate pass transistor logic. The

transistor level implementation of parallel prefix adders based on degenerate

logic used to speed up the binary addition and more flexible to perform addition

of higher Order bits in complex circuits.

Tools Used : PYXIS: Schematic editor. Eldo: Circuit simulation using SPICE simulator.

Work Experience:

Organization: RV VLSI Design center, Bangalore

Designation: Layout Design Engineer

Duration of Project in

Months: Mar 2014 to Sep 2014

Projects:

Company: RV VLSI Design center, Bangalore

Title: Design of 9 track 90nm standard cells

Duration: 3 weeks

Role: Layout Design of Standard Cells

Team Size: 1

Description: Standard cells are elementary objects used to design complex logic circuits. A

standard cell can be a logic gate like AND, OR, NAND, XOR etc... Or can be

storage device like Flip flop implemented by using logic gate. Height of Standard

cell given by the physical design team.

Tools Used : ICstudio to design layout. PYXIS: Schematic and Layout editor.

CALIBRE: To check DRC & LVS.

Deliverable/Challenges 1.Placing the complete layout within the given PR-Boundary, by maintaining all

Faced: DRC rules.

2. Making the layout as optimized as possible by Source & Drain sharing.

3. Placing metal pins on grid by maintaining proper distance undergoing

compatibility checks.

4. Routing is difficult in complex layout because only metal1 is allowed for

routing in standard cells.

Title: Design Of 2 Stage Differential amplifier using 180nm technology

Duration: 2 weeks

Role: Layout Design of 2 Stage Differential amplifier

Team Size: 1

Description: Design of 2 stage differential amplifier consists of 8 MOS transistors. Floor

plane of circuit is done by considering the placement of input and output ports,

current source and signal flowing. In layout design Placement of transistors is

done by maintaining all matching techniques. I used guard rings in layout design

to avoid the latch-up problem.

Tools Used : ICstudio to design layout. PYXIS: Schematic and Layout editor.

CALIBRE: To check DRC & LVS

Deliverable/Challenges 1. Floor plan of layout by considering all matching techniques.

Faced: 2. Making common centroid.

3. Making inter digitization.

4. Avoid Latch-up & Electro Migration problem.

5. Avoid metal routing across active gate region to reduce the parasitic.

Title: Design of 7 track 28nm standard cells

Duration: 2 weeks

Role: Layout Design of Standard Cells

Team Size: 1

Description: Standard cells are elementary objects used to design complex logic circuits. A

standard cell can be a logic gate like AND, OR, NAND, XOR etc... Or can be

storage device like Flip-flop implemented by using logic gate. Height of

Standard cell is constant. Dummy poly is needed for both sides of poly gate. In

28nm technology there is no compatibility rule for placing the metal pins.

Tools Used : ICstudio to design layout. PYXIS: Schematic and Layout editor.

CALIBRE: To check DRC & LVS

Deliverable/Challenges 1. Making the layout as optimized as possible by Source & Drain sharing.

Faced: 2. Placing poly’s and contacts on the grid.

3. Routing is difficult because only metal1 is allowed to routing in standard

cells.

Title: Layout design of Leaf cells of SRAM memory compiler

Duration: 2

Role: Design layout for SRAM

Team Size: 1

Description: SRAM stands on Static Random Access Memory. Six Transistor memory cell is

used in the design of SRAM. The leaf cells of SRAM are Array, Sense amplifier,

Din, Dout, Pre decoder, Final decoder, Control block and Scan block. In this

project the layout design of all leaf cells of SRAM are designed by using 7 track

28 nm standard cells. Finally SRAM architecture is designed by connecting the

all leaf cells with proper connections.

Tools Used : ICstudio to design layout. PYXIS: Schematic and Layout editor.

Calibre: DRC, LVS & PEX check.

Deliverable/Challenges 1. Floor plan of leaf cells is difficult to reduce the layout area by using

Faced: minimum metal layers.

2. Making proper distance considerations to all input and output ports of leaf

cells for automatic connections in the top block.

3. While connecting higher metals if one layer is missing under it i.e. M1, Via1,

M2, Via2 it causes opens in circuits.

Achievements:

• Published National and International Journals on my Academic project.

• Attended International Conference to give presentation on my Academic project.

Personal Profile:

Name :Adilakshmi Siliveru

Date of Birth : 3/May/1990

Address :#35 Nandini layout B.Narayanapura,Bangalore - 560016

Father Name : S.Krishnamurthy

Nationality : Indian

Sex : Female

Languages known : English,Telugu

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