Ganesh jadhav

A/p-Pimpalwadi

Tal-Rahata Dist-Ahmednagar Email:

acgeqb@r.postjobfree.com

M.H, India - 423109

Mobile: +91-996*******

+91-973*******

Summary of Qualifications

> Good understanding of the ASIC and FPGA design flow

> Extensive experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog and UVM

> Very good knowledge in verification methodologies

> Experience in using industry standard EDA tools for the front-end

design and verification

VLSI Domain Skills

HDL: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification - SVA

TB Methodology: UVM

EDA Tool: Questasim and ISE

Domain: ASIC/FPGA front-end Design and

Verification

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional

Coverage, Synthesis,

Static Timing Analysis.

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

June2014 - Oct 2014

Bachelor of Engineering, Sharadchandra Pawar College of Engineering,

Otur(Pune) University of Pune,

Maharashtra, India

Discipline: Electronics and Telecommunication

Engineering

Percentage: 67.45% First Class with distination

Year:

May 2014

HSC:62.47% Year : June 2010

SCC:76.15% Year :June 2008

Experience

Project Intern, Maven Silicon

Five months experience in front end design and verification

June 2014 - Oct 2014

VLSI Projects

[1] Router 1x3 - RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and

routes them to one of the three output channels, channel0, channel1 and

channel2.

Responsibilities:

> Architected the design

> Implemented RTL using Verilog HDL.

> Architected the class based verification environment using system

Verilog

> Verified the RTL model using SystemVerilog.

> Generated functional and code coverage for the RTL verification sign-

off

> Synthesized the design

[2] Daul Port RAM Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tool: Questasim

Description: The dual port ram in project the data can be write and

read at

Same time can be verifed.

Responsibilities:

> Architected the class based verification environment in UVM

> Verified the RTL module with single master and single slave

> Generated functional and code coverage for the RTL verification sign-

off

Engineering Project

B.E project : GSM based digital energy meter with smart card

Description :

This project is based on principle of "pay and use

".

In presently energy meter has number of drawback

like measurement of unit, electricity theft,man

power .

The above all drawback can be solve this project .

It's measurement efficiency is high,it identify the

theft of electricity and reduce the man power .

In this project user can recharge through mobile or

smart card or online.

In this project in, if the user balance is lower

than particular level then buzzer on.

This type of energy meter is used user then we not

need to pay the bill in MSBE center.

In this project in smart card is use because the

rural area in not a sufficient range for GSM.

In a feature scope of this project is use like a

Dish TV network, Only need of MSBT is develop the

one server

Used software : Keil u vision, proteus.v7.10.

Used Programming Language : Embedded C.

Mini Project 1 : Smart solar charger

Description : In this project use solar panel it generate some

amount of voltage this voltage can be store in the

battery in day time .

The store voltage can be use to many small

application in day or night time.

If the battery is charge of 10v after then

automatically stop the charging.

This project is also use as multimeter it show the

voltage of battery or other battery.

It is save the money .

It 's not required the external power .

Used software : Keil u vision, proteus.v7.10.

Used Programming Language : Embedded C, Assembly language;

COMPUTER PROFICIENCY/SKILL SET

Operating System Windows XP//7/8/

Programming Language C,Assembly lang. Embedded lang.,

Verilog,System Verilog,UVM, MATLAB

Web Technology HTML.

Software MATLAB,Keil u vision,Xiline 12.2,

proteus.v7.10,TC,Questasim

EDUCATIONAL QUALIFICATIONS

Degree College / Institute Board % of Year of

/University Marks Passing

B.E(E&TC) Sharadchandra Pawar Pune 67.45 2014

College Of Engineering

T.E(E&TC) Sharadchandra Pawar Pune 52.60 2013

College Of Engineering

S.E(E&TC) Sharadchandra Pawar Pune 58.46 2012

College Of Engineering

F.E(E&TC) Sharadchandra Pawar Pune 55.66 2011

College Of Engineering

H.S.C(12th) Shri Saibaba jounir Pune 62.36 2010

College Shirdi

S.S.C (10th) Shri Chhatrapati Pune 76.43 2008

Shambhuraje Madhyamik

vidyalay Pimpalwadi

Gender Male

Date of Birth 12st June 1990

Marital Status Unmarried

Nationality Indian

Languages known English,Hindi &Marathi

Area of interest Software, Hardware, Researching

New technology, vlsi technology,

embedded system, Chip design

Date :

Place: (Jadhav Ganesh Dilip)

PERSONAL DETAILS

Contact this candidate