CURRICULUM VITAE

Priyank Jitendrakumar Joshi

Address:

Email: acged7@r.postjobfree.com 104-Crystal Rocks, 4th cross,

Email: acged7@r.postjobfree.com Bilekahalli, Bannerghatta rd.,

LinkedIn: in.linkedin.com/pub/priyank-joshi/93/31/698/ Bangalore-560076

Passport no: K7058366

OBJECTIVE

Result oriented and dynamic professional with wide exposure in ASIC verification. Sound

knowledge of verification tools and methodologies and logic design. Looking for a position

as an ASIC verification/design engineer in a prestigious organization.

OVERVIEW

Good understanding in Digital logic design & Electronics fundamentals

•

Good understanding of the ASIC/FPGA design flow

•

Experience in Verilog HDL to write synthesizable RTL, self-checking test benches&

•

Test benches in system Verilog

Very good knowledge on Verification methodologies(UVM)

•

Experience in using industry standard EDA tools for the Front-end Design and

•

Verification

EXPERIANCE

Maven Silicon softech pvt.ltd

Designation: VLSI trainee

My work over here is used to work on live verification projects as well as guide students who

is working on projects

Year: AUG 2013 till to date

P ROFESSIONAL QUALIFICATION

Bachelor of Engineering in Electronics and Communication

Gujarat Technological University, Gujarat

Aggregate: 71.25%

Masters in VLSI & EMBEDDED Systems

KIIT University, Odisha

Percentage: 81.20%

TOOLS & TECHNICAL SKILLS

HDLs : Verilog

HVL : System Verilog

Verification Methodologies : Coverage Driven Verification

TB Methodology : UVM

Protocols : SPI

EDA Tools : Modelsim and Xilinx-ISE,cadence

Domain : ASIC/FPGA Design Flow, Digital Design

Methodologies

Knowledge : RTL Coding, FSM based design, simulation,

Code Coverage, Functional Coverage,

Synthesis, Static Timing Analysis

Operating systems : windows & Ubuntu

VLSI PROJECTS

Dual Port RAM - RTL design and verification

HDL : Verilog

HVL : System Verilog

TB Methodology : UVM

EDA Tools : Modelsim, questa-Verification Platform and Xilinx-ISE

Description :

Implemented the Dual port RAM using Verilog HDL independently

•

Verified the RTL module using Verilog & system Verilog

•

Architecting the class based verification environment using UVM

•

Generated Code coverage & Functional coverage for the RTL verification sign-off

•

Synthesized the design

Router 1 3 design and verification

HDL : Verilog

HVL : System Verilog

TB Methodology : UVM

EDA Tools : Modelsim, questa-Verification Platform and Xilinx-ISE

Description :

The router is a device that forwards data packet between computer networks, It is an

•

OSI Layer three routing device, It drives an incoming packet to an output channel

based on address field contained in packet header.

Architected the design and described the functionality using Verilog HDL

•

Verified the RTL model using Verilog

•

Generated code coverage for the RTL verification sign-off synthesized the design

•

Architecting the class based verification environment using UVM

•

Verification of the RTL module using UVM

•

Generation of functional coverage for the RTL verification

•

Serial Peripheral Interface (SPI) verification

TB Methodology : UVM

EDA Tools : Modelsim, questa-Verification Platform and Xilinx-ISE

Description :

The serial Peripheral Interface (SPI) is a full-duplex, Synchronous, serial data link, It

•

enables communication between microprocessors and peripherals and/or inter-

processor communication.

Architecting the class based verification environment using UVM

•

Verification of the RTL module using UVM

•

Generation of functional coverage for the RTL verification

•

ACEDEMIC PROJECTS

Communication with the person using ZIGBEE wireless IEEE standard Protocol along with

PIC microcontroller

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge.

Place : Bangalore Signature : Priyank joshi

reference on Request.

Contact this candidate