Fariduddin Masud

B.G. road, MAX PG Email:

acge6n@r.postjobfree.com Bangalore-76

Mobile: +919*********

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CAREER OBJECTIVE:

To work in VLSI Domain where performance is rewarded with new responsibilities with knowledgeable environment

and to grow along with the organization as a core member of the same.

SYNOPSIS:

A Trained Candidate in VLSI with B .Tech Degree in Electronics and Communication Engineering from West Bengal

University of Technology with the knowledge of VLSI Design and verification and practical electronics circuit design.

SUMMARY OF QUALIFICATIONS:

• Good understanding of the ASIC and FPGA design flow.

• Experience in writing RTL models in Verilog HDL and familiar with System Verilog and UVM.

• Knowledge of Digital electronics and CMOS fundamentals.

ACADEMIC QUALIFICATIONS:

DEGREE/ EXAMINATION UNIVERSITY/BOARD YEAR OF PASSING MARKS

B. Tech (Electronics and WBUT 2014 68.6 %

Communication

Engineering)

Higher secondary WBCHSE 2010 69%

Secondary WBBSE 2008 86.87%

VLSI DOMAIN SKILLS:

HDLs: Verilog

HVL: System Verilog (basic)

METHODOLOGY: UVM.

EDA Tools: Questa Sim, XILINX ISE Simulator.

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, Digital system design, synthesis, Simulation and verification

OPERATING SYSTEMS: Windows and Linux

VLSI PROJECTS WORKED ON:

1. SOFTWARE DEFINED RADIO PROCESSOR ARCHITECTURE (SDR):

DESCRIPTION: This tiny digital modulator chip can modulate three different type of modulation

schemes (BASK, BPSK & BFSK) according to the requirement. This single chip can be used as a

processor for a software defined radio and anywhere in communication systems where different types of

modulations are required.

RESPONSIBILITIES:

• Key role in System Architecture

• Implemented and verified it using VERILOG-HDL

• Synthesized the design

• Tool used XILINX 14.1 simulator

2. DESIGNED A LOW POWER DIGITAL CARRIER SIGNAL GENERATOR (DCG)

DESCRIPTION: This single chip will generate the output in form of digital signal instead of analog

carrier signal generator with very low power and low cost. This chip can be used to design any low power

digital modulator like BASK, BFSK, BPSK as a carrier signal generator.

RESPONSIBILITIES:

• Key role in System Architecture design according to logic criteria and implemented the required

mathematics for architecture.

• Implemented and verified the design using VERILOG-HDL

• Synthesized the design

• Tool used XILINX 14.1 simulator.

3. DUAL PORT RAM: Designed the RTL of a dual port RAM and verified its functionality

4. FIFO DESIGNED: Designed a FIFO and Verified its functionality.

ACHIEVEMENTS AND AWARDS :

• Selected as a Head promoter for West Bengal for 'SPOKEN TUTORIAL PROJECT', IIT-

BOMBAY (an open source software project funded by MHRD, India) to promote and use of

open source software. Handled more than 100 engineering colleges and institutes across WB and

effectively arranged more than 200 workshops within a couple of months and handled thousands

of students and faculties from various institutes.

• Gave lots of new business Ideas to organize workshops in a very cost effective way and some

ideas became model for various states of India.

• Worked as a mentor for newly appointed promoters for other states to guide them for organizing

and managing events and workshops effectively.

• Performed the best among all the promoters in India and awarded as a 'STAR PROMOTER' from

IIT-BOMBAY.

REFERENCES:

On Request

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