JYOTHI M.H.

H.No – ***, **/*A, Vidyanagar,

Hathalagerinaka, Gadag – 582 101.

+91-998*******

acgdnb@r.postjobfree.com

OBJECTIVE:

Seeking a position to utilize my skill and abilities with an opportunity for professional growth where team

spirit and personal skills are recognized and rewarded.

EDUCATIONAL QUALIFICATIONS:

MASTER OF TECHNOLOGY (VLSI DESIGN AND TESTING)

COLLEGE: B.V.B College of Engineering and Technology, Hubli

UNIVERSITY: Visvesvaraya Technological University. Belgaum.

YEAR: 2014AGGREGATE: 85.61% (CGPA : 9.31 )

BACHELOR OF ENGINEERING (ELECTRONICS AND COMMUNICATION)

COLLEGE:R.L.Jalappa institute of technology,Doddabalapur

UNIVERSITY: Visvesvaraya Technological University. Belgaum.

YEAR: 2012 AGGREGATE: 76.57%

TECHNICAL SKILLS:

Programming Languages :C, VHDL, Verilog,ARM / µC.

Technical Subjects :VLSI, Microcontroller (8085,8056),Logic Design, Circuit

design,embedded c.

Tools known :Xilinx ISE14.2, Cadence IC5141, Mat lab 7.11, KeilµVision4.

PERSONAL ATTRIBUTES:

Hard worker, Good Time Management, Punctuality & Motivate others.

INDUSTRIAL TRAINING:

Title : Layout Optimization Techniques for High PSRR LDOs.

Company : Sankalp Semiconductors Pvt. Ltd. Hubli.

PROJECT SUMMARY:

Project #1: M.Tech Project (Main)

Title: "Design and Simulation of Second Order Sigma Delta Modulator for ADC”.

Description:This project presents the design of second-order sigma delta modulator for low frequency

analog signal at the supply voltage of 2.4V using the switched capacitor integrator, operates at a

frequency of 1MHz, using 1.2V reference. The design has been implemented in Cadence tool,

UMC180PDK in 180nm CMOS technology. Under Sankalp Semiconductors Pvt. Ltd. Hubli.

Environment: Cadence tool, UMC180PDK in 180nm CMOS technology.

Operating system: LINUX

Role & Responsibilities: Design and Implementation

Project #2: M.Tech Project (Mini)

Title: "Layout Optimization of Low Drop-Out, High PSRR LDO for RF Application ".

Description:This project presents several optimized layout design methods and the optimized LDO

layout. The whole layout design of LDO regulator manually uses Cadence tool, UMC180PDK in 180nm

CMOS technology.

Environment: Cadence tool, UMC180PDK in 180nm CMOS technology.

Operating system: LINUX

Role & Responsibilities: Layout Optimization

Project #3:B.E. Project (Main)

Title: “Simulation of Biometric Authentication Using Fast Correlation Of Near Infrared Hand

Vein Pattern”.

Description:This project proposes a novel technique to analyze the infrared vein patterns in the back of

the hand for biometric purpose. The system consists of following individual steps: Data Acquisition,

Image Enhancement, Vein Pattern Segmentation and Matching.

Environment: Mat lab

Operating system: Windows 2007

Role & Responsibilities: Design and Implementation.

M.Tech Course Projects:

Characterization of CMOS circuit and analysis of second order effects using cadence.

Testing Of Gyrator-C Active Inductor Using MOS Transistor.

Analysis of low power VLSI circuits using ng-spice.

ACHIEVEMENTS:

Academic Excellence Award in BE 2008-2009.

Second place in hockey at Taluk level.

PRESENTATION:

Finalist in India Electronics semiconductor Association Super project contest organized in the

field of ESDM (Electronic System Design & Manufacturing) at Intel Technology Bangalore.

HOBBIES & INTERESTS:

Playing Chess, Listening music, drawing & Reading novels.

EXTRA CURRICULAR ACTIVITIES:

NCC

SPORTS

KARATE

PERSONAL DETAILS:

Name : Jyothi.M.H

Father’s Name : Hanumantappa L.Mundasad

Date of Birth : 08-04-1991

Nationality : Indian

Languages Known : English, Kannada and Hindi

I hereby declare that the above given details are true to the best of my knowledge.

Place: GADAG

Date: (JYOTHI M.H.)

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