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basics of verilog,systemverilog and uvm.

Location:
Bengaluru, KA, India
Posted:
October 15, 2014

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Resume:

KEERTI Email id :

acgdlt@r.postjobfree.com

Contact No : +91-812*******

CAREER OBJECTIVE

To learn the work culture and procedure of my job profile. Willing

to grow professionally with the organization while being innovative,

resourceful and flexible.

ACADEMIC PROFILE

> M.Tech - VLSI Design and Embedded systems with aggregate 76.125% from

BNM Institute of Technology, VTU, Bangalore in 2014.

> B.E - Electronics and Communication Engineering with aggregate 79.57%

from Appa Institute of Engineering and Technology, VTU, Gulbarga in

2012.

> P.U.C with 82.33% from Muktambika PU College, Gulbarga in 2008.

> S.S.L.C with 78.88% from Mahadevi girls high School, Gulbarga in 2006.

TECHNICAL SKILLS

> Proficient knowledge in Verilog and System Verilog.

> Good knowledge of Universal verification methodology (UVM)

> Proficient in Xilinx and Model Sim tool flow

PROJECT DETAILS

In M.Tech

Implementation of AES Algorithm for secured Data Transformation

Description : In this project, We have implemented a

cryptography security AES algorithm which works on a

128 bit data encrypting it with 128 bits of keys for

ensuring security

Team size : 2

Tools used : Xilinx ISE 9.1i

Design and Analysis of Low Power CMOS Charge Sharing Dynamic Latch

Comparator using 180nm Technology

Description : In this project, We have designed a Comparator that

combines the features of both resistive dividing network

and differential current sensing comparator Hence imrove the

pesformce of comparator by reducing the the propogation

delay.

Team size : 2

Tools used : Cadence Spectre Simulator.

Development of Memory Monitor for LPDDR2 Memory Controller in UVM

Description : In this project, I have designed Memory monitor.

Memory monitor is verification component which monitors all

the signals at Design under Verification (DUV)-Memory

interface. DUV used in this project is LPDDR2MC (low power

double data rate2 memory controller). Memory model chosen

is DDR2 SDRAM S2 and S4 device which can be configured to 4

or 8 banks. Whenever any of the masters request for read,

write, activate, or precharge, memory controller generates

these commands. To analyze which command is executed and to

know which bank is accessed memory monitor is necessary.

Monitored information is made available to other

verification component in UVM environment through TLM ports

Team size : 1

Tools used : ModelSim SE 10.1c

In BE

Bus Arrival Prediction Technology

Description :This project aims at providing the

efficient local bus transport system. The bus arrival time,

number of vacant seats and which stop the bus has arrived

will be displayed on LCD display present at the bus stops.

If there are any bus failures and route diversion, it will

be displayed on the LCD display and the reason is also

displayed for the same.

Team size : 4

Tools used : KEIL uVision,Flash magic.

STRENGTHS

> Enriched with the ability to learn new concepts and technology within

a short span of time.

> Self-motivated, hardworking and goal oriented with a high degree of

flexibility, commitment and optimism

PERSONAL PROFILE

Name : Keerti

Father's Name : Nagendra Ujjeli

Sex : Female

Date of Birth : 30-05-1990

Marital Status : Single

Nationality : Indian

Languages known : Kannada, English,Hindi

Hobbies :

Pencil sketch, reading novel,

listening music.

Permanent Address : C/O

S.S.Hiregouda,

H-No 11-195 Upper

Lane Brahampur

Gulbarga(T)-585103

Gulbarga(D), Karnataka(state)

DECLARATION

I hereby declare you that all the above details are true and correct to

the best of my knowledge and belief. I promise you that I will be a

Dynamic Personality who is very truthful and loyal to contribute to

the organization's goal.

Place:

Yours truly,

Date:

Keerti

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