Jieting Yang

**** ******** ***. *** ****, Houston, TX 77006 281-***-****

acgd85@r.postjobfree.com

EDUCATION

Rice University, Houston, TX GPA: 3.63

Master in Computer Engineering and minor in Computer Science, May 2014

Imperial College London, London, United Kingdom Degree Honor: Merit

Master of Science in Analogue and Digital Integrated Circuit Design, Nov 2011

Dalian University of Technology, Dalian, China Grade: 85%

Bachelor of Science in Electrical Engineering and Automation, Jul 2010

Curriculum highlights: Data Structure, Advanced Object-Oriented Programming and Design, Databases,

Algorithms, Computer Architecture, Compiler Construction, Communication Networks, Programming

Basis

TECHNICAL SKILLS

Languages: Java/J2EE, SQL, T-SQL, UML, RMI, C, C++, HTML, CSS, JavaScript, and XML

Development Tools: Eclipse, SQL Server, PLSQL Developer, Xcode, MySQL

Operating Systems: Linux, Windows, OS X

PROGRAMMING EXPERIENCE

Database System Projects Apr 2014- May 2014

• Built a small Java/JSP web application on top Google's App Engine framework, using Google's Cloud

SQL as a backend

• Extended the given parser and performed appropriate semantic checks on the input SQL in Java

• Translated the output of the parser into relational algebra and executed the relational algebra in Java

Advanced Object-oriented programming in Java Projects Aug 2013-Dec 2013

• Generated multiple strategy balls by implementing various design patterns including MVC, Factory,

Command, Observer-Observable, Strategy, Composite in Command-dispatching BallWorld Project

• Implemented transmitting remote data packets and adhered to specific designed API and Use Case by

applying the technology of RMI and two layers of MVC, etc in RMI ChatAPP Application Project

• Created a game with separate server and client dependent on the World Wide Map technique,

extended visitor design pattern, etc in World Wind Java Game Project

Instruction Scheduler Project Nov 2013

• Developed a Java program to schedule ILOC block in order to avoid hardware interlocks

• Reduced instruction running time by 40% by creating the dependence graph and rescheduling

instructions according to it

LL (1) Parser Generator Project Oct 2013

• Constructed a Scanner, a Parser and a LL(1) Parse Table Generator which produces first set, follow

set, first plus set, productions and LL(1) table in YAML format in Java

• Determined the input grammar is a LL(1) grammar by applying Recursive Descent Parser Algorithm

Local Register Allocator Project Sep 2013

• Implemented a local register allocator in both top-down method and bottom-up method in Java

• Achieved a shift in the number of registers correlated to a shift in instruction running time

VLSI Design Project Sep 2012-Dec 2012

• Designed a systolic array co-processor for matrix factorization and solution for systems of linear

equations using Xilinx System Generator tools, Xilinx ISE tools, along with Synopsys DC Ultra

• Applied algorithm-specific VLSI processor architectures and used Cadence SOC Encounter tools

• Performed High-level DSP algorithm simulation and code (Verilog) generation by aid of AutoESL

HONORS & ACTIVITIES

• Received an award of excellent graduate of the Dalian University of Technology 2006-2010

• Volunteer for Dalian Charity Federation Volunteers Branch Dec 2008

• Secretary in Student Union of Dalian University of Technology Sep 2006-Jul 2007

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