VISWANATH KADIYALA

((: +91-903*******

+91-903*******

E-mail: acgd4u@r.postjobfree.com

Career Objective

To work with a result oriented organization that seeks an ambitious and

career conscious person where acquired skills will be utilized towards

continuous growth and advancement.

Strengths

Strong analytical aptitude

Quick Learner

Self-motivated and hard working

Professional Details

. 1.6 months of Real time work experience (Intern+Real time).

. Worked as a ASIC Engineer at SiconTech, Hyderabad till February 2013.

. June 2012 - September 2012 Contract employee at Synopys Inc,Bangalore

(Contract from Sicontech, Bangalore)

. June 2011 - June 2012 Internship at STMicroelectronics Greater Noida.

Technical Skills

Language : Verilog.

Operating System : Linux(Redhat)

Electronic Tools : Synopsys VCS,Hpsice,DC Compiler,Spyglass

Scripting language : Shell, Perl

Area's Of Intrest : Synthesis(ASIC),Physical design,CMOS

Analog design

Academic Qualifications

M.S (VLSI-CAD) - Manipal Centre for Information Sciences,Manipal

University, 8.04 CGPA

B.TECH (ECE) - TRR COLLEGE OF ENGINEERING JNTU-HYDERABAD WITH FIRST CLASS

Project Details

Projects Undertaken at STMicroelectronics

Regression using SPYGLASS in Frontend Kit

The main aim of our project is to run regression tasks

using SPYGLASS rules(lint checking) using ST internal Kit,called FEKit .

Contribution:

. Development of automation script using perl and C-shell.

Execute the run using spyglass tool.

. Testing of FEKit while setup and sourcing to execute the

run.

. Understanding the spyglass rules set.

June 2011 to July 2012

Role : Project Trainee

Environment : Linux

Language : Verilog,,Shell Script,

Tool : Spyglass,DC Compiler

Projects Undertaken at SYNOPSYS

1) DC-MONET COMPATABILITY CHECK

Description :

. Worked on the UPF with synospys new EDA tool command

validation(MONET).

Contribution :

. Validated some testcases over MONET and DC Compiler.

. Validated tcl commands for MONET tool.

July 2012 to September 2012

Role : UPF checks on large RTL and NETLIST designs.

Environment : Linux(redhat)

Tool : Monet (synopsys)

Tool : Spyglass,DC Compiler

Projects Undertaken at MCIS Manipal

1) TSPC LATCHES AND FLIPFLOPS CHARACTERIZATION

Description:

This project aimed to check the characterstics of TSPC flipflops

and latches.

Contribution :

. Netlist simulations using Hpsice.

. To extract the setup and hold times using Hpsice Bisection

algorithm.

Environment : Linux

Tool : Hspice(synopsys)

2) Ethernet packet generator

Description:

This project aimed to generate the Ethernet packet frame, of

specified bytes and transmission of the given packet,which

uses IEEE 802.3 protocol.

Contribution:

. Verilog coding and compilation using VCS(synopsys) tool.

Tool : VCS

Platform : Linux

References

Atul Nauriyal

Technical Leader

Digital Design Flows -Frontend

Test chip design flows

STMicroelectronics Pvt Ltd.

Greater Noida

acgd4u@r.postjobfree.com

012*-*******

Shekhil Hassan T

acgd4u@r.postjobfree.com

Design Engineer, Synopsys Inc,

Bangalore.

(: 903-***-****

Personal Details

DOB - 24-12-1988

Hobbies - Reading Novels, WORLD CINEMA,Telugu literature.

DECLRATION

I hereby declare that all the above-mentioned details are true to the best

of my knowledge and belief.

Viswanath Kadiyala

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