Sathish N

#**/**, *** *****, *** Cross, Raghavendra Layout,

Silver Springs Road, Behind Yashomathi Hospital,

Kundalahalli Gate, Bengaluru -560037

Phone:- +91-886*******

E-mail:- acgcwb@r.postjobfree.com

CAREER OBJECTIVE :-

To secure a challenging position where I can effectively

contribute my skills as Hardware Engineer, possessing competent Technical

Skills.

AREAS OF INTEREST :-

. Digital Design.

. Analog and Mixed Signal IC Layout Design.

. Microcontroller.

EDUCATION :-

Master of Technology (M-Tech)

Major : Digital Electronics.

Institute : CMR Institute of Technology,

Bengaluru.

University : Visveraraya Technological University.

Percentage : 79.41%.

Post Graduation : June 2013.

Bachelor of Engineering (B.E.)

Major : Electronic Electronics and

Communication.

Institute : SEA College of Engineering and

Technology, Bengaluru.

University : Visveraraya Technological University.

Percentage : 73.28%.

Graduation : June 2011.

Pre-University

Major : Physics, Chemistry, Mathematics,

Electronics.

Institute : Sri Bhagwan Mahaveer Jain College,

Bengaluru.

University : Pre-University Board, Karnataka.

Percentage : 73.83%.

Graduation : May 2007.

SSLC/10th

Institute : Lady Vailankanni High School,

Bengaluru.

University : SSLC Board, Karnataka.

Percentage : 79.04%.

Graduation : May 2005.

ACADEMIC PROJECTS :-

M-Tech Project

Digital Pulse Processing and Pulse Height Spectrum in X-Ray

Spectroscopy Using FPGA carried out at ISRO -ISITE, Bengaluru.

B.E. Project

Digital 3-Axis Gyro Package carried out at DRDO-ADE, Bengaluru.

TECHNICAL SKILLS :-

1. Programming Languages : VHDL, Verilog, MATLAB, C.

2. Operating Systems : Windows, Linux.

3. Tools : Cadence Virtuoso 5.1.4, Cadence Virtuoso 6.1,

Xilinx-ISE, Libero, Calibre, Assura,

MATLAB.

EXPERIENCE :-

June - 2013 - July 2014 : MosIC Solution, Bengaluru.

IC Layout Engineer(Engineer I).

Roles & Responsibility

. Standard Cell Layout Design and Characterization.

. Worked on Layout of Digital Blocks like Ring Oscillator, Shift

Register.

. Worked on Layout of Analog Blocks like OP-AMP, BGR(Band Gap Reference),

Switching Capacitor Bank.

. IO-Ring Design.

ACHIEVEMENTS :-

. Successfully streamed one complete chip .

. Designed SPI Protocol and implemented successfully on FPGA.

. Converted the Assura DRC rule file to DivaDRC rule file.

PROJECTS:-

. ROIC for Accelerometer for SITAR-STARC on TowerJazz TS18SL(180nm)

technology.

. True Random Number Generator( TRNG) for SITAR-STARC on Sitar1um

technology.

STRENGTHS:-

. Quick and eager to learn new things.

. Get along with people and believe in team work.

. Confident.

. Adaptive.

. Positive attitude.

HOBBIES:-

. Circuit Designing.

. Listening to songs.

. Watching movies.

. Reading Novels.

PERSONAL DETAILS :-

Name : Sathish N

Father's Name : Narayana Rao S

Date of Birth : 24-OCT-1989

Nationality : Indian

Languages Known : Kannada, English, Hindi, Tamil and Telugu.

E-mail ID : acgcwb@r.postjobfree.com

Phone : 886*******, 28525888

DECLARATION:-

I hereby declare that the above furnished details are true and

correct to the best of my knowledge.

Date:- ( SATHISH

N)

Place:-Bengaluru

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