K.NAVEEN KUMAR E-mail: acgagn@r.postjobfree.com

Mobile: 903-***-****

To achieve a position to utilize my skills and abilities that offers and helps in the Professional growth and

development of the Organization with sincerity and determination. Aim to occupy a leading, responsible

and challenging position in an organization that can provide good opportunities, ensure all-round

development and encourage independent and innovative thinking.

PROFESSIONAL SNAPSHOT

Completed two projects on physical design implementation flow with using EDA tools Cadence -

encounter (1 year), Synopsys-ICC (6 months) with 65nm, 40nm technologies.

Working experience in ASIC Place and route, physical verification, static timing analysis and

physical design development.

Implemented Multi Node Methodology clock tree synthesis.

Participated in the block level full chip timing closure (STA) of multi-million gate ASICs.

Developed PERL/Tcl scripts to handle various requirements of algorithms and data manipulation

Gained good Knowledge in subjects like Digital design backend, advanced static timing analysis,

semiconductor device modeling, and Low power VLSI design.

ACADEMIC CREDENTIALS

Advanced Diploma in Physical design from SHASRTA MICRO SYSTEMS.

Masters of science VLSI and Embedded system from Jawaharlal Nehru technological university

Hyderabad in 2013 with distinction with 78%

B. Tech (EEE) from TKR College, JNTU, Hyderabad in 2011 with 65.6%.

Intermediate from NARAYANA Junior College, Hyderabad in 2006 with 73%.

SSC from Naagarjuna High school, Hyderabad in 2004 with 75%.

EDA TOOLS USED

Synopsys:

IC complier(Physical design)

Prime time(Static timing analysis)

Design compiler (Synthesis)

VCS(Functionality and simulation checking)

Cadence:

Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis

Encounter Timing System –Static Timing Analysis and Crosstalk Analysis

RTL Compiler- Logic Synthesis.

ACADEMIC AND TECHNICAL PROJECTS

Master’s Thesis Project 1:

Title: Skew Aware Multi node clock tree synthesis.

Implementation: Developed and Implemented algorithm to reduce Skew using Multi Node

clock tree Synthesis Methodology

Specification:

Design : ARM CORE (open source)

Design Flow : Block

Tools : Encounter/ETS

Gate Count : 120k

No. of Clocks : 3

Technology/Layers : 40nm (NANGATE)/8 Metal Layers

Roles and Responsibility:

Physical design:

Analyzed traditional clock tree synthesis.

Developed an algorithm for Multi Node clock tree synthesis using tcl/perl

Able to achieve 20% skew reduction and reduction in number of buffers used.

Project 2:

Title: Physical Design Implementation of DTMF chip

Design flow : Hierarchy

Tools : First Encounter- Cadence

Gate Count : 60k

No. of Clocks : 2

Frequency : 129MHZ, 64MHZ

Technology/Layers : TSMC 180nm/6 Metal Layers

Roles & Responsibility:

Full Chip Implementation, timing, power and Block level P & R.

Block Partition and Integration.

Starting from Floor plan to GDS and delivering the Timing closed and DRC/ LVS

clean database to chip integration team for tape out at block level database to

chip integration team for tape out at block level.

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