Cell Phone: 503-***-**** or 971-***-**** E-mail:

acg55y@r.postjobfree.com

CAREER SUMMARY

** ***** ********** ** *** semiconductor industry providing process

engineering support in both manufacturing and research and development

environments. Very hands-on and collaborate well with both equipment

maintenance and operations.

WORK EXPERIENCE

Staff Engineer (Etch), Jireh Semiconductor Hillsboro, OR

05/12 - 07/14

. Responsible for oxide, metal etch and outgoing wafer quality control.

. Backup engineer on CD and film thickness metrology, poly Si etch, ash,

solvent strip and wet etch processes.

. Developed and implemented optimized in-situ wafered and waferless

cleans to improve oxide etcher mean time between cleans and reduce

defectivity.

. Implemented endpointed etch processes to improve process repeatability

and tool capacity.

. Reviewed inline SPC charts and equipment down issues daily. Reviewed

and evaluated electrical parametric data as required to insure process

stability.

Staff Engineer (Yield), ON Semiconductor, Gresham, OR

10/10 - 05/12

. Responsible for edge engineering including chips, breaks and scratches

and standardization of defect trends across all technologies.

. Evaluated defectivity trends real time and recommended tool/process

restrictions and engineering involvement when warranted.

. Updated defect database and educated technicians on expedient

determination of likely defect source during a process excursion. Main

backup contact for all in-fab defect issues.

Senior Process Engineer (Etch), Maxim Integrated Products Beaverton, OR

05/04 - 10/10

. Responsible for oxide etch and metal etch on Performed ongoing

projects to reduce inline and end of line scraps, improve inline and

parametric CPKs, increase tool utilization and availability.

. Involved in projects to optimize existing processes and process

development for new device integration.

Field Service Engineer, Tokyo Electron America Hillsboro, OR

01/03 - 05/04

. Responsible for maintenance, troubleshooting and repair of TEL Unity

II and Telius SCCM etchers.

. Tracking of MTBF, root cause analysis, critical spares and setup a

troubleshooting database.

Chemistry Instructor, Portland Community College Portland, OR

09/02 - 04/03

. Responsible for teaching general chemistry and laboratory instruction.

Sr. Process Engineer (litho&etch), Integrated Device Technology

Hillsboro, OR 06/97-10/01

Litho:

. Responsible for CD metrology and maintenance of dark field layers.

. Oversaw a resist conversion project to improve process latitude and

reduce costs.

Etch:

. Responsible for ash and wet etch/strips.

. Evaluated and implemented ash reduction to reduce costs.

. Optimized solvent strips to reduce defectivity and improve tool

utilization.

. Provided additional support to oxide, poly and metal etch modules.

Lithography Process Engineer, Nortel Ottawa, Ontario, Canada

01/95 - 05/97

Optoelectronics

Advanced Processing group

. Responsible for the development and demonstration of a 0.1 um grating

printing and etch process for InP DFB laser array fabrication.

. Evaluated phase shift masks for both conventional and surface emitting

DFB laser arrays.

. Designed and modified a contact aligner for off-axis illumination of

phase shift masks.

. Evaluated a commercial holographic aligner for DFB laser array (0.1um)

and SAW device (0.25um) lithography.

. Evaluated and implemented a new resist with BARC process to increase

yields on discrete DFB lasers.

Development Engineer, Nortel Ottawa, Ontario, Canada 01/92 -

12/94

Silicon Components Group.

. Responsible for patterning of ferroelectric related materials by wet

and dry etching and lift-off techniques.

. Evaluated and purchased a plasma etcher for patterning ferroelectrics.

. Designed a test mask set to evaluate the integration of ferroelectrics

onto Si ICs for NV-DRAM and on-chip de/coupling capacitors.

. Prepared precursor solutions and characterized spin-on techniques to

prepare films of ferroelectric PZT, conducting Ruthenium dioxide and

inorganic resist/H2 barrier materials.

. Studied the effect of substrate preparation and solution composition

on electroless copper deposition.

SKILLS

Experienced with LAM 9600/DFM metal etchers, LAM 4400/4520/XL, TEL UnityM

and AMAT Centura oxide etchers, AMAT P5000 and DPS poly etchers, Mattson,

Aura 1000 and 2000, Axcelis, Gasonics 3510 and ULVAC ashers, Semitool acid

and solvent tools, AME 8115, Tegal 904e, AMAT MarkII, MxP+ and DPS metal

and LRC Alliance, SEZ single wafer wet etch and Wet sinks. Experienced with

Opal and Hitachi CD SEMs, Tencor UV1050, Thermawave 2600/5200, ASML, GCA

and Canon steppers and SVG & DNS tracks, KLA 2139, Tencor AIT1, Rudolph

August AXI Macro inspection tool, JEOL SEMs and KLA-Tencor eV300. Knowledge

of Kaizen(6 sigma), lean manufacturing, DOE and SPC.

EDUCATION

Ph.D. Chemistry Carleton University, Ottawa, ON, CANADA, 1996

Thesis title - "Photoinduced Electron Transfer in Chromophore-Quencher

Complexes Designed for Metal Centered Chemistry" Thesis Supervisor - Dr.

R. J. Crutchley

B.S. Chemistry, Carleton University, Ottawa, ON, CANADA, 1986

Graduated with High Honours

PATENTS

Maxim: 7,966,722

Nortel: 6,337,032; 6,066,581; 5,728,603 and 5,358,889

Contact this candidate