Kartik Pathak

**** ********** ****

Parsippany, NJ 07054

PH: - 973-***-****

Email: - acg36t@r.postjobfree.com

Objective: - Looking for a challenging position in the area of Asic design

and Verification engineering.

Skills:-

. Programming Languages: C, C++, MATLAB, HSPIC simulation, VHDL, Basic

Scripting in Linux

. Tools: Modelsim (mentor graphics), VHDL, Montor graphic EDA, OP-NET

17.5, Quartus II 9.1, MATLAB simulator, Oracle VM Virtual box

. Operating Systems: Windows XP, 7, 8, Windows server 2008, 2012, Unix,

Linux (Red hat Cent Os), Ubuntu, Mac, Android, PXE (Preboot eXecution

environment)

. Software / Applications : MS Office, Adobe Photoshop, Lotus Notes,

outlook, MS project, visio

. Networking: Switches, Routers, Hubs, Servers, Racks, Firewalls, LAN,

WAN, TCP/IP, DNS, VoIP, PPP

. Mobile Communication: GSM Architecture, CDMA 2000, BTS, BSC, MSC

. Design/Drawing Tools: Ulti-board (PCB Design), Multisim (Circuit

Design), Pcad (Antenna Simulation Software), Solid drawing editor.

. Assembly Languages: 8085, 8086, 80386 Microprocessors & 8051, PIC

Micro controllers

Education:-

Master of Science, Electrical Engineering Sep

2011 - May 2014

New Jersey Institute of Technology (NJIT), Newark, NJ

GPA: - 3.7/4.0

Bachelor of Engineering, Electronics and communication

June 2004 - June 2008

Gujarat University, Ahmadabad, Gujarat, India

GPA: - 3.96 / 4.00

Relevant course work: VLSI design I, Semiconductor devices, VLSI design II,

Computer architecture, Computer networking lab, Control system design, DSP

lab, Random signal analysis and Linear systems, Engineering Mgt, Project

control.

Learning tool: Verilog, System Verilog

Projects at NJIT: -

. Implement a parallel algorithm in VHDL for "Object recognition in

image" proposed in IEEE. Use TSMC 0.18 micron technology.

Successfully done pre and post synthesis simulations. Created a

testbench.

. Design a chip for 32 bit subtraction using 2's complement in TSMC

0.18 micron technology for 850 Mhz data output rate. Use CLA (Carry

Look Ahead Adder) logic, Shift register, Domino logic to meet

requirements. Design layout to reduce parasitic and cross check with

spice simulation

. Design a chip for 32 bit decoder in TSMC 0.35 micron technology: -

Design schematic and layout in mentor EDA tool check the simulation

in ELDO and also extract parameters from Caliber PEX.

. 16 point IFFT using Quartus II. Define algorithm in VHDL, perform

functional simulation and implement code on FPGA board.

. Design network for corporation using OP-NET. Modeling, configuration

and performance analysis of customized network for corporation using

op-net modeler.

. Furuta pendulum and Magnetic levitation (Matlab) in control system

design,

. Real time speech signal analysis (Matlab) in random signal processing

Project during Bachelor:

. Ultra Sonic Distance Meter: To learn microprocessor timer, counter and

assembly programming

. PC BASED FUNCTION GENERATOR: To understand digital to analog

conversion and interaction of circuit board to PC and oscilloscope

. FM Receiver

Professional Experience:-

Hardware Validation Engineer, Since May 2014

ZT Systems, Secaucus, NJ, USA

Job description: -

As a Hardware validation Engineer my role is Internal Server R&D Hardware

validation

Responsibilities:-

. Projects: DDR3 RAMS, DDR4 RAMS, LRDIMMS, RAID card, HBA, Intel CPU

(Haswell plateform, IV Bridge, Sandy Bridge, Grantly), Mezz cards,

BIOS, BMC, SSD, HDD, NIC, Kauri6T, Saturn14, Humbold14, etc

. Interfacing with architecture, design, system-level simulation,

platform, BIOS and system engineering for a high degree of

collaboration and leverage in all phases of the design process

. Evaluate test specifications, requirements, strategies and

methodologies for electrical validation and platform level testing

. Coordinate test effort preparation and track requirements, schedules

and actions

. Review, track, document and summarize test results

Co-OP in solutions engineering group, June 2012 to May 2014

PANASONIC SYSTEM COMMUNICATION OF NORTH AMERICA, Harrison - Technology

center, NJ, USA

Job description: -

As a Co-op Engineering my role is assist senior engineers in development of

new products, test methodology (IP 65) (MIL-810G), conduct test, research

solutions, etc.

Responsibilities:-

. Projects: Plug-in PC, Tough book (cf-31) and Tough pad (M1, G1), 3rd

party printers for tough pad, GPS application for cf-31, Network

Scanner, Intel education laptop and tablets, collaborative class room,

etc

. Test different applications (Megstrip, barcode scanner, etc) on

different operating systems. Ex. Android, windows

. Conduct test per requirements, Prepare test procedure, make changes

in prototype modules.

. Develop applications / fixture to test products, work with 3rd party

to trouble shoot the technical issues.

. Conduct temperature test, Vibration test, Drop test, water (IP-65)

test, hing test, keyboard test, passmark performance test, burn-in

test, bench mark test, etc on different products.

Electronics Engineer

PPI-TIME ZERO, Paterson, NJ, USA

Job Period: Oct 2010 to April 2012

Company Profile: PPI is leading name in Electronics manufacturing services.

An industry based on providing contract design, manufacturing and product

support services on behalf of OEMs. Traditional services include PCB

assembly, box-build and testing.

Job description: -

As Electronics engineer my role is to prepare methodology of project

process. Assist in production and quality department.

Responsibilities:-

. Modify circuit, drawing, components as per customer requirement

. Prepare control (Method) book for production

. Design electronic work station for out-sized projects

. Develop applications for employee to make production easier, faster

and qualitative

. Train employee for new projects and help them on production floor

Technical support engineer

Scientech Technologies Pvt Ltd, Indor, MP, India

Job Period: June 2008 to Dec 2009

Job description: -

As a Technical support engineer my role varies between R&D departments to

marketing department based on requirements.

Responsibilities:-

. Troubleshoot Educational electronic trainer equipments

. Hands on experience on developing application for specific Electronic

Trainer Boards

. Savvy with installation and commissioning of cutting edge heavy

Electrical Equipments at client location

. Install variety of new equipments and trained employees

. Provided technical session to marketing officials about different

product, features and its core competence as compared to market

competitors

Electronics and Communication Intern

Sonic Technology Pvt Ltd, Gandhinagar, Gujarat, India

Internship Period: January 2008 to June 2008

Responsibilities:

. Hands on training of design and development of Printed Circuit Board

(PCB)

. Learned ORCAD to develop single and multi layered PCBs

. Experienced the manufacturing process of developing single and multi

layer PCB

. Developed two layered PCB for FM Radio Receiver using ORCAD

. Sooner the company officials recognized my grasping skills and

dedication to work, and assigned me to design and prepare working

plans, scale drawings and charts in detail for 2 client projects

. In designing the scale drawings, performed basic calculations to

determine strength of materials, layout of charts and information

gathering on structural requirements of a material.

SEMINARS DELIVERED

. Optical fiber as a means of communication

. Wi-Fi, Wi-max & Broadband communication(IETE VODODARA CENTER)

SEMINARS Attend

. Low Power Deep Submicron Designs by R K Chadha of e-Silicon corp

. 3D Integrated Circuit Technology by Mukta Farooq of semiconductor R&D

center, IBM

Work authorization status: - Legally authorized to work as a US Permanent

Resident since Dec, 2009. Citizenship acquisition is in process, expected

to be citizen by Jan, 2015.

Contact this candidate