* ********* ******

Career Objective:

Seeking a challenging job where I can apply my technical skills and serve

to the best of my

potential, in exchange for career guidance, training, and opportunity for

advancement.

Academic Profile:

(2010-2013) B.TECH ECE Sri visvesvaraya institute of technology &

science college,Mahabubnager.Ap. 70%

(2006-2009) DIPLOMA IN ELECTRONICS SMTTKR Polytechnic pamarru, Ap.

60%

(2005-2006) SSC Vijaya Convent High School, Challapalli, Ap. 72%

October 2013 Advanced Diploma in VLSI Design & Technology Indian

institute of vlsi design & Training -Bangalore, Karnataka

Academic Project:

Project1: "Boundary Detection in Medical Images Using Edge Following

Algorithm Based on Intensity Gradient And Texture Gradient Features".

Project2 : "Generalized Substitution-box".

Seminar : Seminar on "Wireless Sensors Networks For Health Care

Applications".

Technical Skills:

HDLs: Verilog

Scripting Language : Perl,TCL

EDA Tool: RTL Compiler, Conformal Low Power,

Cadence Encounter, Olympus

Domain: ASIC/FPGA Design Flow, Digital Design

methodologies

Perl .

> finding the cells and instances in given netlist:

> Hierarchical instantiation in the netlist:

> Cell accumulated area

reading the netlist and getting the cell area from

respective library file

> Delay in timing report

perl script to find the total delay (net and cell).\

> In/out/inout port

finding input,output and inout port in a given design

> pin connected to given net

for a given net how which pins are connected to it

scripts on lib, lef, def:

scripting on library, Tech LEF and Macro LEF files using Perl

> Finding number of routing layers and cut layers present in the tech

LEF file:

In a given tech LEF finding the Layer type and count for it.

> number of sequential and combinational cells present in the .lib file:

based on the timing type, to distinguish between seq and comb

cells

> number of 'don't use cells' present in the library:

checking the cells which has attribute of dont_use as true.

> find out the pins connected to given net from DEF file

Synthesis and Formal verification :

EDA Tool used: RTL Compiler

Scripting language: Tcl

. Synthesis of hierarchical design

. Writing script and tool based commands in tcl for running synthesis in

RTL Compiler for a given designAnalysis of reports generated

Timing, area,gates and power reports in different stages of

synthesis (pre and post optimization)

. Generating .do files for LEC analysis

Dofile generation and using it for equivalence check using conformal.

. Appending the clock gating attributes to design.

Inserted clock gating attributes for low power synthesis

Physical design:

> Implemented designs in Olympus and Encounter

> Implemented block level in encounter

> Macro placement based on connectivity and fly lines

> Implemented designs in Cadence Encounter from Floor plan to GDS

> CTS with buffer and inverter

> Checks at every stage of flow

> Fixing timing issues related to skew and setup, hold in ets

> Analyzing the timing reports and fixing the issues.

> Fixing DRC violations(Antenna,spacing,width-length) in olympus..

Personal Profile:

Name : Mandalapu Manasa

Father Name : M Sambasivarao

Mother Name : M jhansi lakshmi

Gender : Female

Date of Birth : 13 march, 1991

Nationality : Indian

Marital Status : Single

Permanent Address : Sivarampuram,

Mopidevi

(MD)

krishna

(DT)

D.No.:7-16-

1,

Pincode

-521126.

Declaration :

The above mentioned details are true and correct to the best of my

knowledge.

Mandalapu.manasa

Contact this candidate