LOPAMUDRA PATTANAYAK

E-mail:acfu0s@r.postjobfree.com

Contact No: +91-814*******

PROFILE:

Currently associated with RV-VLSI Design Centre as Design Engineer, Bangalore

from Sep 2013 to till date. Having around 1 year’s of experience in VLSI Design and

Verification.

JOB RESPONSIBILITY:

Have hands on experience in using industry standard EDA tools for the front-end

design and verification.

Have hands on experience on System Verilog Verification and worked on developing

verification environment using SV.

Possess good knowledge on UART protocol.

Have good knowledge and work experience on Altera-FPGA.

Knowledge on Linux.

Good understanding in UVM.

EDUCATION:

M.Tech in VLSI Design and Embedded system from Kalinga Institute of Industrial

Technology,Odisha in 2013 with 8.87 CGPA .

B.Tech in Electronics and telecommunication from Biju Patnaik University of

Technology,Odisha in 2010 with 7.89 CGPA .

TECHNICAL SKILLS:

Hardware Description

Verilog

Languages

Hardware Verification System Verilog

Languages

EDA Tool QuestaSim, ModelSim

Scripting Language Shell(Make file)

Operating System Linux,Windows7, Windows XP

PROJECT EXPERIENCE:

PROJECT#1

Title : Verification of mini UART

Technology Used : QuestaSim 10.0c

Team Size :1

HVL : System Verilog

Description:

The mini-UART is a fully functional, synthesizable, Universal Asynchronous

Receiver Transmitter soft core, ideal for embedded processor applications or system-on

programmable-chip. The core is based upon the ultra-compact micro-UART core. A dedicated

synchronous microprocessor bus interface module is wrapped around the micro-UART. All

internal operations of the mini-UART can be controlled and programmed by the

microprocessor bus. The external microprocessor can program the baud rate. A status register

can be polled in real-time to keep progress of the transmitter as well as the receiver.

PROJECT#2

Title : Verification of SPI Master Core

Technology Used : QuestaSim 10.0c

Team Size :1

HVL : System Verilog

2

Description:

SPI (Serial Peripheral Interface) Master core is a synchronous serial interfaces used to

provide economical board-level interfaces between different devices such as

microcontrollers, DACs and ADCs and others. This SPI Master core is compatible with SPI

(a trademark of Motorola Semiconductor), microwire/plus (a trademark of National

Semiconductor) as master and at the host side, the core acts like a WISHBONE compliant

slave device.

Roles and Responsibilities:

Verified the protocol using class based SV Test bench.

Verified the master-slave signal transactions.

Generated functional coverage for the verification

PUBLICATIONS:

An efficient approach of low power and high speed BIST: using priority algorithm,

Lopamudra Pattanayak, G L Kumar Moganti, S Khare, publication in the proceedings

by IEEE conference, which is ICACT 2013.

DECLARATION:

I, hereby, declare that the information stated here in the above is true to the best of my

knowledge and belief.

Place: Bangalore. (Lopamudra Pattanayak)

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