USHASREE K

H.no : **-**-***/*, Plot no.***,

Mail ID: acfq6c@r.postjobfree.com

Road no.11, Alkapuri colony,

acfq6c@r.postjobfree.com

Nagole,

Hyderabad,India

Cell No: 080********,098********

CAREER OBJECTIVE

To work in an organization that will utilize and enhance my skill sets in

the field of CMOS IC Circuit design, Layout and ASIC / FPGA design /

Verification and applications.

AREAS OF INTEREST

Digital IC Design

ASIC Implementation

FPGA Implementation

Analog and Mixed Signal IC Design

EDUCATION

Degree Institution Percentage/CGPA

M.Tech (VLSI) VIT 76.2

(2011-2013) University-Vellore,India

B.Tech (EIE)(2006-2010) Bhoj Reddy Engg College 63.87%

for

Women(BRECW)-Hyderabad,I

ndia

Intermediate(10+2)(2006- Narayana Junior 87.1%

2010) College-Hyderabad

Secondary (S.S.C.)(2004) Nalanda Vidya Bhavan 86 %

High

School-Hyderabad,India

PAPERS PUBLISHED AND CONFERENCES ATTENDED

Presented and published a paper titled "VLSI Implementation of Single

Precision Floating Point Unit using Verilog" in 2013 IEEE conference on

information and Communication Technologies (ICT 2013) held during 11th and

12th April 2013,organised by Noorul Islam Centre for Higher Education,

Tamil Nadu, India.

Presented a paper titled "ASIC implementation of space wire router ip

protocol for space wire applications" at 4rth international science and

engineering technology (SET) conference organised by VIT University,

Vellore, Tamilnadu, India.

Presented a paper titled "Performance of VCO for 4G Applications using S

parameters" at 3rd international science and engineering technology (SET)

conference organised by VIT University, Vellore, Tamilnadu, India.

FINAL SEMESTER PROJECT

> ASIC Implementation of Single Precision Floating Point Unit using Verilog

Group Strength:1

This project presents high speed algorithms for ASIC implementation of a

floating point arithmetic unit which can perform addition, subtraction,

multiplication, division, square root and trigonometric functions on 32-bit

operands that use the IEEE 754-2008 standard. This has been implemented in

Cadence RTL compiler, sim vision and SOC Encounter EDA tools using TSMC

180nM and 90nM process technology.

MAJOR PROJECTS

> Performance of VCO for 4G Applications using S parameters

Group Strength:3

Here a wide band CMOS VCO for 4G applications is designed for a tuning

range of 4.02 GHz to 5GHz centred at 4.5GHz; obtained with a tuning voltage

of 1 to 15V using the Cadence in Cadence RTL compiler, sim vision and SOC

Encounter EDA tools in TSMC 180nM and 90nM CMOS process

> ASIC Implementation of Space Wire Router IP Protocol for Space Wire

Applications Group Strength: 3

The project is based on space wire (SpW) standard for satellite on-board

networks proposed by The European Space Agency .The link interfaces and the

routing matrix of the SpW router are modelled in Verilog HDL and has been

implemented in Cadence RTL compiler, sim vision and SOC Encounter EDA tools

using TSMC 180nM process technology.

> ASIC Implementation of Stop Watch Style Timer

Group Strength: 1

The project is to design a stopwatch-style timer with a clock of a known

frequency and displaying between 00.00 and 99.99 seconds on four common-

cathode 7-segment displays which has been implemented using RTL compiler,

sim vision and SOC Encounter tool in Cadence for 180nM technology.

> Low Power Flash ADC with Reduced Comparators

Group Strength: 3

Here in this project a 4 bit flash ADC is implemented which uses less

number of comparators compared to conventional flash ADC that uses total of

eight comparators and is implemented in Cadence using 90nm technology.

TECHNICAL SKILL SET

Operating Systems : Windows, Linux.

Languages known : Verilog HDL, 8051 Assembly language, basics of C.

Tools Known : Cadence Virtuoso, SOC Encounter, RC-RTL

compiler, NC Sim in CADENCE, Quartus II-Altera, Quartus II-Model Sim, TINA

TI, Keil, Multi Sim.

ACTIVITIES AND ACHIEVEMENTS

Participated in IIIT Hyderabad, India "ROBOCAMP" six day workshop in 2008.

School head for social services committee and raised funds for social

activities.

Participated and qualified in maths, science, green Olympiads and many

inter school competitions.

Won in quiz competitions and cultural activities at school and college

level.

STRENGTHS

A dedicated, equally effective as working independently.

A Team player as well, with good communication and written skills.

HOBBIES

Reading Novels, dancing, playing chess.

PERSONAL PROFILE

Name : Ushasree K

D.O.B : January 4, 1989

Gender : Female

Husband's Name : Suchetan Reddy K

Father's Name : G. Sathyanarayana Reddy

Mother's Name : G. Mani

Permanent Address : H.no:11-13-350/2, Plot no.150, road

no.11, Alkapuri

colony,

Nagole, Hyderabad, India

Contact No. : 080********, 098********

Languages : English, Hindi, Telugu

Nationality : Indian

DECLARATION

I hereby declare that all the evidences given above are true to my

knowledge and belief.

Place: Hyderabad, India

(K.Ushasree)

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