CURRICULUM VITAE

A.JOHN STERRETT NOEL

acfm2j@r.postjobfree.com

Mobile: 900-***-****

* ****** ********* **********

M.TECH .VLSI DESIGN – (2012 -2014)

B.TECH.Electronics & Communication Engineering – (2008-2012)

PROFESSIONAL TIME HISTORY

September 9th 2013 –

INTERN-System on Chip STMicroelectronics,

February 14th 2014.

Verification greater noida

(6 months)

Worked in an IP, system on chip SPC570S50Lx which is built on Power

microcontroller Architecture technology and integrates technologies that are

important for present and future automotive applications

SPC570S50Lx targets applications such as ABS and airbag in car, both of which

require a high safety integrity level.

Have Launched Regression Testing and verified few failed Test cases

Worked on IP’S such as MEMU,FCCU etc

Written few Test cases for the Design Blocks

RTL design

PROFESSIONAL SOFTWARE SKILL SET

Operating system : Microsoft windows, M.S. Office, M.S. excel.

•

Language : C, C++, data structures (certification done by NIIT)

•

Hardware language : verilog, VHDL & basics of system verilog

•

Design : HTML design

•

Tools known : cadence NC-SIM, Xilinx, Pspice, model sim,AUTO CAD

•

Layout tools : Basics of CADENCE- virtuoso, Micro wind.

•

PROJECTS SUMMARY

Title : System on Chip Verification on Automotive Products group

Role : INTERN

RESPONSIBLITIES:

To launch Regression Testing

Prepare a report on failed, running and passed test cases

Verify the failed test cases of the IP assigned to me

Change the test cases for the new IP and new Protocols assigned

SCOPE :

System on chip SPC570S50Lx which is built on Power microcontroller

Architecture technology and integrates technologies that are important for today’s

and tomorrow’s automotive applications.

SPC570S50Lx targets applications such as ABS and airbag in car, both of which

require a high safety integrity level.

OVM verification methodology is Adopted

TOOLS USED:

CADENCE –NC SIM

ACADEMIC MEASURE

M.TECH. (VLSI DESIGN) 2012-2014 8.06 CGPA

Sathyabama University, Chennai

B.TECH.(Electronics & Communication) 2008-2012 6.92 CGPA

Karunya University, Coimbatore

H SC

Mahatma Montessori, Madurai 2008 84.08 %

SSLC

Noyes Matriculation, Madurai 2006 75.81 %

PERSONAL PROFILE

Name : A.JOHN STERRETT NOEL

Date of Birth : 18.12.1990

Father’s Name : A.ARJUNAN

Marital status : Unmarried

Languages Known : Tamil, English

Nationality : Indian

Address : “HIGHFIELD” Door NO: 4-21-18,

Plot No s-10, Park town, 1st Street,

P&T Nagar, Madurai-625017

REFERENCES

MR RIPAN BANSAL

Hardware Design Engineer,

ST.Microelectronics, Greater Noida,

Email:acfm2j@r.postjobfree.com

Dr.K.V. KARTHIKEYAN

Assistant Professor,

Sathya Bama University, Chennai

Email: acfm2j@r.postjobfree.com

DECLARATION

I hereby declare that all the above given information are true to the best of my

knowledge and I am committed to giving my best for the growth of the company .

Place: A.JOHN STERRETT NOEL

Madurai

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