CURRICULAM VITAE

ABHISHEK A. BHATT

Email id: acfl91@r.postjobfree.com Ramananjaney Layout,

Contact no. +91-903*******, 987-***-**** Marathahalli Bridge,

Bangalore - 560037

Karnataka, India

Objective

To pursue a highly challenging career to reflect the technical and interpersonal skills gained in the field of

VLSI. Highly motivated to take new ideas into action and to do research in VLSI designs.

Professional Experience

Synopsys India Pvt. Ltd

VLSI Engineer,Contractor (8-Months)

Key Responsibilities

• Development of Test Plans with different complicated scenarios.

• Created and Simulated Different Test Cases based on System Verilog Assertions .

• Defined System Verilog Assertions in Module Block,Checker Block,Program Block, Interface

block, Generate block, Vunit block, function block,task block, with different combination .

• Validated System Verilog Assertion results with different assertion types,assertion controls,

assertion system task,assertion system functions, bind statements .

• Find VCS Tool bugs regarding System Verilog Assertions.

• Regression work for developed test cases and bench marks.

• Resolved customers issue regarding System Verilog Assertions .

Projects

Validation of System Verilog Assertions Enhancements on VCS tool

Synopsys India Pvt Ltd, Bangalore

• System Verilog Assertion semantic “s_eventually” validated on VCS tool

• System Verilog Assertion semantic “$assertcontrol” validated on VCS tool.

• System Verilog Assertion “DVE GUI Controls” validated on VCS tool.

• System Verilog Assertion “ ucli-Asserthier Controls “validated onVCS tool

AMBA AXI using Verilog

Description:

(MS 1stSEM Project) Using Verilog HDL. Designed AXI Bus, In This Several masters can

able to handle several slaves at a time. For data transfer address burst technique was also

implemented. AMBA AXI Bus mainly used in System on Chip . This design Simulated in

Synopsys VCS and Timing Analysis done using Design Compiler

Ethernet Protocol using System Verilog

Description:

(MS 2nd SEM Project) Ethernet Protocol was implemented using System Verilog.

Using wishbone interface, data transfer of 10gbs between MAC(Media Access Control) and

Physical Chip was made possible and successfully simulated in Synopsys VCS tool and Timing

analysis done using Design Compiler.

Audio Steganography Using Verilog

Description:

A B.E. Final Year Project in which audio stenography device was implemented using Verilog.

In this digital Audio stream data was hidden using Register control Unit

Encryption/Decryption, Pseudo random number Generator .

Static Timing Analysis done for Multi Clock and Multi cycle design

Description:

In this Project using Design Compiler I have analyzed FIFO deign. In which FIFO Read and Write

operation performing two different clock cycles.

Designed and verified Layout of different types of Flip Flops and Gate.

In this Project using HSPICE and Magic Layout tools for design layout of all types of Flip Flops

and gate with 90 nm.

Technical Skill

Tools – Synopsys VCS, Synopsys Design Compiler,Synopsys HSPICE, MAGIC Layout,Model sim,

Xilinx-ISE, Quartus, Matlab

Languages – OVM(basics),System Verilog, Verilog,VHDL, C, C++, PERL,Assembly Language

Education

Class/Course Name of Institute Board/University Year of Passing Marks%

MS 2011-13 8.29/10

Manipal Centre for

Manipal University, Manipal

Information Science

(VLSI - CAD) CGPA

BE R.K.College of

(Electronics & Engineerin&Technology, Saurashtra University, Rajkot 2006-10 65.12%

Rajkot

Communication)

H.S.C S.G.dholakiya high

Gujarat Board 2005 66.88%

school,Rajkot

L.B.S vidhyalay,

S.S.C. Gujarat Board 2003 67.14%

Rajkot

Research Interest

Digital Design and Verification, Low-power VLSI, Static Timing Analysis, Physical Design, FPGA

Designs.

Paper Presented

• Carbon Nanotube Transistor(CNT)

Description: Presented in Manipal university . In which I have discussed carbon nanotube

transistor working Principles and compare with the CMOS.

• Multi Voltage Island Scheme

Description: Presented in Manipal university. In which I have discussed Multi Voltage Island

Scheme how reduce the Power consumption in designs and how to implement this technique in

Low Power VLSI.

Extra Curricular Activities

• Participated in “open hardware” at “Technofora-2008”,Nirma university, Ahmedabad.

• Participated in “open hardware ” at ”Xplode-2008“,L.D.engineering college Ahmedabad.

• Attended “FPGA system design using EDA tools” workshop conducted at Manipal Centre for

information science,Manipal.

Personal Profile

• Name : Abhishek Bhatt

• Father Name :Ashok Bhatt

• : 29th Sep 1988

Date of birth

• Languages Known : English, Hindi, Gujarati

• Nationality : Indian

Reference

Name:Mr.Neelabja Dutta

R&D Manager

Synopsys india Pvt. Ltd. Bangalore

Email id: acfl91@r.postjobfree.com

Contact Number:+91-994*******

Contact this candidate