RESUME

KIRAN

PATEL

Mobile No. : +91-940******* E-mail Id: acfkzi@r.postjobfree.com

+91-915*******

Objective:

Intend to build a successful career in semiconductor domain with immense learning

opportunities, growth prospect and make maximum use of my strengths and technical

knowledge contributing to the growth of company.

Academic Record:

Examination Branch College University Result

Electronics & Hasmukh

Communication Goswami College Gujarat

71.00%

B.E. engineering of Engineering, Technologica

(CGPA*: 7.6)

(Graduate- Vahelal l University

2012)

Laljibhai

VLSI System

Chaturbhai Gujarat 86.80%

Design

M.E. Institute of Technologica (CPI**: 9.18)

(Post Graduate

Technology, l University (GTU 1st Rank)

- 2014)

Bhandu

(CGPA*= Cumulative Grade Performance Index, CPI** = Cumulative Performance Index)

Examination Board Month/Year Marks

SSC GSHSEB March 2006 86.57%

HSC GSHSEB March 2008 73.00%

Core Competency:

Complete knowledge of Digital Logic Design Concepts

Understanding of Testing and Verification of VLSI design

Basic knowledge of Transistors Fundamentals and CMOS Fabrication process

Knowledge of Power Efficient VLSI Design

Understanding of Applied Algorithm for VLSI CAD

Good understanding of ASIC design flow and FPGA design flow

Have knowledge of Analog VLSI design concepts (DLL, PLL, Comparator, ADC,

DAC etc.)

Worked on 90nm and 180nm CMOS Technology

Basic knowledge of Antenna and Wave propagation

Basic knowledge of Data communication and Networking

Working knowledge of Linux Commands

acfkzi@r.postjobfree.com

Good Management, personal & organizational skills

Tools Used :

Mentor Graphics EDA tools : Eldo, IC Studio

Xilinx : Xilinx ISE, ModelSim

Tanner EDA : T-SPICE

CST Microwave Studio : Design Antenna & check performance

Hardware Description Language : VHDL, Verilog

Programming Languages : C,C++

Operating Systems : Windows (7, XP, VISTA), LINUX

Others : Matlab, Microwind, Multisim

Academic Projects:

1. Title: “Characterization and Simulation of Delay Locked Loop in DSM Technology”

Tools Used: Eldo & IC Studio from Mentor Graphics

Specification: Vdd=1.5v, fope=1.5GHz

Description: In this project, I have achieved low jitter (68 ps) and faster locking time

(15 Cycles) of Delay Locked Loop at 1.5GHz. The accuracy of the DLL depends on

all the four blocks; Voltage controlled delay line (VCDL), Phase frequency detector

(PFD), charge pump (CP) and Low pass filter (LPF). I have designed VCDL by using

current starved inverter and PFD based on NOR gate. The second order low pass filter

helps to improve stability of DLL and remove current spikes at output. Combination

of both VCDL & PFD work as the required functionality.

2. Title: “Compact printed slot wearable Antenna for medical Application”

Tools Used: CST Microwave Studio

Specification: Design frequency=5.8 GHz, Circular type patch

Description: In this project, I have achieved antenna working in larger band.

I have used patch (circular) technology for conducting part of antenna.

Co Curricular Activities:

I have taken Part to organize the Technical Festival and Cultural week in every year

in my college.

I have participated in Movie maker event in “Innovata 2011” held in our college.

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I have participated in TEQNIX-2012 held at LDCE “DAKAR RALLY” events.

I got award for Best Faculty in a Day in competition at Teacher day.

I have arrange exhibition on “Kargil: a victory and pride” on 5th & 6th April, 2014.

Strengths:

Interested in Technical Discussions

Ability to become leader in a Team

Always willing to learn new technologies

Basic knowledge of technical subjects

Able to adjust in any environment

Problem solving skill

Personal Details:

Name : Patel Kirankumar Ishvarbhai

Age : 24

Gender : Male

Nationality : Indian

Date of Birth : 18 February, 1991

Present Address : A/404, Flamingo Empire, Nr. Maratha Mandir, Pune-411021.

Permanent Address : AT & post:-Satlasana, Near limdi chock

Ta:-Satlasana, Dist:-Mahesana, State:- Gujarat, Pin:-384330

Languages known : English, Gujarati, Hindi

Hobbies : Browsing Internet, Playing Volley-Ball, Technical Discussion

Declaration:

I hereby declare that the above mentioned information is correct and I bear the

responsibility for the correctness of the above mentioned particulars.

Place: Pune

[Kiran Patel]

acfkzi@r.postjobfree.com

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