NATIONAL INSTITUTE OF TECHNOLOGY

TIRUCHIRAPPALLI

INDIA

BHARAT NALLURI

Male, Indian, 27

H.No: 2-473 nagaram (p.o)( m.d), Guntur(d.t), A.P .

Contact: (M): 081********

E m a i l : acfkxj@r.postjobfree.com

CARRER SUMMARY

Highly Self Motivated Engineer with 2+Teaching experience .

Having strong fundamentals.

Proficient in HDL.

Good exposure to tools

Possess good interpersonal, communication and analytical skills .

EDUCATION

Degree/ Year of Percentage

School/Institute Board/University

Examination Passing /Grade

National Institute Of National Institute Of

M.Tech

2014 Technology, Technology, 7.1 CGPA

(VLSI SYSTEMS) Tiruchirappalli Tiruchirappalli

St.Ann’s college of

B.Tech

2008 engineering and J.N.T.U,Hyd 66.04%

(E.I.E) technology

Board of Intermediate

Sri viveka junior

Class XII 2004 Education,Andhra 80.10%

College,Tenali

Pradesh

Board of Secondary

Class X 2002 Z.P.H School,kolavennu Education,Andhra 86.66%

Pradesh

GATE 2012 (IN) score of 714.

Department of Training and Placement, NIT Tiruchirappalli 620015

Telefax : +91-431-******* e-mail: acfkxj@r.postjobfree.com, acfkxj@r.postjobfree.com

PROJECT WORK

PG Projects

Phase1 Dynamic partial reconfiguration for OFDM Transceiver on FPGA board.

(Ongoing, funded project at NIT Trichy).

Description:

A novel scalable and runtime dynamic partial reconfigurable FFT architecture for

different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture

for two different FFT points is realized using modified Single -path Delay Feedback (SDF)

pipelined architecture via a proper data flow reconfiguration .It can support 64, and 128

points.

Contribution: My responsibilities included:

Identifying top level module

High level design (HLD)

Verification of modules in verilog.

Dumping into the FPGA tool kit.

Verification with CHIPSCOPE.

partial reconfiguration using XILINX PLANAHEAD TOOL

Phase2 Reduction of PAPR using the combination of clipping and selective

mapping techniques.

Description:

The Orthogonal Frequency Division Multiplexing is one of the modulation techniques

widely used in the broadband wireless technology. One of the main problems of this

technology is the high peak-to-average power ratio of transmission signal due to the

superposition of many subcarriers. This paper presents a new hybrid peak -to average

power ratio reduction technique, which combines a selective mapping method with the

clipping method.

Contribution: My responsibilities included:

Literature survey

Identifying the problem

Coding in MATLAB

Documentation

Department of Training and Placement, NIT Tiruchirappalli 620015

Telefax : +91-431-******* e-mail: acfkxj@r.postjobfree.com, acfkxj@r.postjobfree.com

INTERESTING AREAS

VLSI TESTING

DIGITAL CMOS DESIGN (with strong basic digital electronics concepts)

ASIC

SOFTWARE SKILL SET

Languages : Verilog HDL

Packages : Mentor Graphics tools - MoldelSim .

Cadence tools - Virtuoso Spectre,

NC Launch,

RTL Compiler.

FPGA tool from Altera - Quartus.

ACADEMIC ACHIEVEMENTS & CO-CURRICULAR ACTIVITIES

Secured 60th Rank in GATE-2012

I had obtained a merit certificate from the District Collector for the S.S.C school first.

WORK EXPERIENCE

Worked as a Assistant professor in Tenali engineering college, Tenali for two years

From 2009 may to 2011 June.

Giving gate training to students

EXTRA CURRICULAR ACTIVITIES

Event coordinator and anchor for two national level symposiums

Presented three papers in national conferences in UG

PERSONAL DETAILS

Father’s Name : Sreenivas

18th August 1987

Date of Birth :

Linguistic Proficiency : English, Hindi,Telugu

Department of Training and Placement, NIT Tiruchirappalli 620015

Telefax : +91-431-******* e-mail: acfkxj@r.postjobfree.com, acfkxj@r.postjobfree.com

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