Madhurima Das

Mobile: +91-983******* ~ E-Mail: acfe22@r.postjobfree.com

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Seeking assignments in Software Development / Application Development with

an organisation of repute

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Summary

< Electronic Design Automation (with C++, VERILOG, SYSTEM VERILOG, VHDL in

LINUX platform) with 5+ years of experience in Software Development,

Testing & Training.

< Currently working in Electra Design Automation Pvt. Ltd., Kolkata:

Contractor of Verific Design Automation, USA as Senior Software Engineer.

< Adept in end-to-end development of software products from requirement

analysis to designing, coding, testing, de- bugging,

documentation and implementation.

< An effective communicator with excellent relationship building &

interpersonal skills. Strong analytical, problem solving & organisational

abilities. Possess a flexible attitude.

< Good team member with helpful and flexible attitude.

< Passion for constant improvement.

< Fast learner with consistent ability to achieve rapid comfort level in

new environments and almost immediately develop optimal solutions.

< Rigorous, quality-conscious contributor with solid analytical and writing

skills.

< Ability to make good decisions in stressful situations.

< Good working knowledge in architecting, requirement analysis, developing

applications using C++

< Core expertise in algorithm development and software design. Unique

expertise in synthesis tools for Verilog and VHDL coupled with in-depth

knowledge and understanding of object oriented programming with C++

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Professional Experience

< Company: Electra Design Automation Private Limited, Kolkata

- Contractor of Verific Design Automation, USA

(www.verific.com)

< Designation: Senior Software Engineer Since

February '09

< Key Result Areas

Technical

Core expertise in algorithm development and software design. Unique

expertise in synthesis tools for Verilog and VHDL coupled with in-depth

knowledge and understanding of object oriented programming with C++.

Proven expertise in complex system architecture (hardware and software), in

EDA tool definition and in EDA Parser tool development which form the basis

of technical solutions provided to answer customers' designing needs.

Operating Systems: LINUX, Windows98/XP/Windows 7

Technologies: EDA (Electronic Design Automation)

Software Languages: C++

Hardware Languages: VERILOG, SYSTEM VERILOG, VHDL

Scripting Languages: TCL

Key Skills: Data Structures, Algorithm

Editors: VI, VIM, GVIM

Debug Tool: GDB, CGDB, EMACS

Memory Management Tool: VALGRIND

Software Tools and Packages: LEX and YACC, Profiling tools, make, CVS,

VCS, ModelSim, NC-VERILOG,

NC-VHDL, DC (Design Compiler), Geometry Extractor,

Swig.

Functional

< Understanding the technical & functional specifications.

< Designing, developing, testing, troubleshooting and debugging of the

applications.

< Managing smooth implementation and testing of the application.

< Providing post-implementation, enhancement and maintenance support to

client for application.

< Unit Test Case preparation and Testing

< Regression Testing

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Assignments Undertaken

Job Description

Electra Design Automation works as a contractor of Verific Design

Automation, USA. Electra Design Automation develops and maintains Verific's

tool. Verific's tool is a COMPILER for hardware description languages like

VERILOG, SYSTEM VERILOG, and VHDL.

Verific's tool builds VERILOG, SYSTEM VERILOG and VHDL Parser Platforms

which enable to develop advanced EDA products. Verific's Parser Platforms

are distributed as C++ source code and compile on all 32 and 64 bit UNIX,

LINUX and Windows operating systems. Verific's Parser Platforms are in

production and development use today at numerous companies worldwide, from

EDA start-ups to reputed semiconductor vendors. Applications vary from

formal verification to synthesis, simulation, emulation, virtual

prototyping, in circuit debug, and design-for-test.

VERILOG, SYSTEM VERILOG, VHDL are parsed and processed in two steps,

analysis and elaboration.

ANALYSIS creates PARSE-TREES and performs TYPE-INFERENCING to resolve the

meaning of identifiers. The Parser/Analyzer supports the entire VERILOG,

SYSTEM VERILOG and VHDL languages, without any restrictions. The resulting

parse tree comes with an extensive API.

ELABORATION supports both STATIC elaboration and RTL elaboration. Static

elaboration elaborates the entire language, and specifically BINDS

instances to modules, resolves LIBRARY references, propagates DEFPARAMS,

unrolls GENERATE statements, and checks all HIERARCHICAL names and

FUNCTION/TASK calls. The result after static elaboration is an ELABORATED

PARSE TREE, appropriate for simulation like applications. RTL elaboration

is limited to the SYNTHESIZABLE subset of the language. In addition to the

static elaboration tasks for this subset, it generates sequential networks

through FLIPFLOP and LATCH detection, and BOOLEAN extraction. The result

after RTL elaboration is a NETLIST, appropriate to applications such as

logic synthesis and formal verification.

Assignments

Clients Handled: Aldec, Altera, Apache, Atrenta, Ausdia, Blue Pearl,

Calypto, DeFacTo, Excellicon, Forte, Intel, Jasper, NEC,

Nvidia, Oasys, Real Intent, Rocketick, Synopsys, Tabula,

Tektronix, Yogitech, Xilinx

< Major Assignments:

o Assignment-1: State Machine Conversion: Analysis Project

Part-1: Implicit to Explicit State Machine Conversion

with Clocking Event for

VERILOG.

Part-2: Implicit to Explicit State Machine

Conversion with Clocking Event for

VHDL.

Part-3: Implicit to Explicit State Machine Conversion

with Event Triggering for

VERILOG.

Details: Convert non-synthesizable VERILOG/VHDL

design to synthesizable one.

o Assignment-2: Graph Optimization :Static Elaboration Project

Details: Optimizing Full Static Elaborated Parse Tree

(graph) depending upon the presence of

hierarchical references.

o Assignment-3: Package Conversion: Mixed Language Project(Mixed

VHDL-VERILOG)

Part-1: Convert VERILOG Package to VHDL Package

Part-2: Convert VHDL Package to VERILOG Package

Details: Over the language boundaries (VERILOG-

VHDL): Convert VERILOG package

to corresponding VHDL package while

importing VERILOG package in VHDL

design. Convert VHDL package to corresponding

VERILOG package while importing VHDL package

in VERILOG design.

o Assignment-4: NETLIST Optimization Project

Part-1: Optimize NETLIST Operators: driven by

constant adder/multiplier

1. Shifter

2. Mux

3. Decoder

Part-2: Optimize adders:

1. if a upstream adder is solely connected

to a downstream adder

2. Merging of two equivalent adders.

Part-3: Constant propagation: Constant propagation on

all NETLIST Operators

(with constant inputs) like Adder, Subtractor,

Multiplier, Divider, Mux, Decoder, Encoder,

Selector etc.

Part-4: Priority Selector: Converting priority selector

to parallel selector and then merging parallel

selectors.

Part-5: Power Operator optimization: Create NETLIST for

VERILOG Power Operator: MATLAB Algorithm.

o Assignment-7: NETLIST Writer Customization Project

Part-1: Flattening NETLIST Operators.

Part-2: Writing NETLIST in different fashion for

VERILOG-95 and SYSTEM VERILOG mode.

o Assignment-8: Convert Recursive Algorithms to Iterative Algorithms

Details: Implement some recursive algorithms (both in

Verific's VHDL and VERILOG branches) to

iterative one: to get rid of recursion stack

overflow.

o Assignment-9: Handing keywords in different Verilog mode: LEX-YACC

manipulation Project

Details: Handing keywords of VERILOG Versions (95, 2001,

2005, SYSTEM VERILOG) by switching flex mode.

Handling ` begin_keywords-`end_keywords.

o Assignment-10: Application Writing: User Interface to control

Verific's parser tool

Part-1: Module Inlining: Flattening of multilevel

modules.

Part-2: Traverse hierarchy: Traverse hierarchy crossing

the language boundary (VERILOG-VHDL Mixed

Language application).

o Others: Apart from the above major assignments: Fixed a number of

VIPERs (id for our product bugs or

enhancements) throughout the 5+ years in this company.

< Team size: Individual

< Role: Developer

< Accountabilities:

o Understanding requirements.

o Analyzing the requirements from technical aspects.

o Development / maintenance of Verific's tool.

o Unit and system testing.

o Implementing workflow/unit cases as per client requirements

and involved in defect fixing.

< Technologies Used: C++, TCL Script, Debug Tools (GDB, CGDB,

EMACS),

Memory Management Tool (VALGRIND)

< Skills Used: Data Structures, Algorithm

< Environment: Linux

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Academic Credentials

2009 Master of Computer Applications from Birla Institute of

Technology, Mesra with CGPA 8.43

2005 BSc (Hons) in Chemistry from University of Calcutta (Bethune College)

with 52.33%

2002 12th from W.B.C.H.S.E with 80%

2000 10th from W.B.B.S.E with 84.88%

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Extracurricular Activities

< Completed 5 year diploma in painting

< Completed 5 year diploma in dancing

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Awards & Achievements

< Was among top 2 in the MCA batch

< Was among top 5 in school

< Won certificates & awards for painting and dancing

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Personal Dossier

Date of Birth: 24th September, 1983

Mother's Name: Mrs. Mitali Das

Father's Name: Mr. Subhendra Nath das

Nationality: Indian

Language Known: Bengali, English and Hindi

Hobbies and Interest: Listening to music, Reading Story Books, Painting

and Dancing

Marital Status: Married

Permanent Address: 25/2/1, Madhusudan Pal Chowdhury First Bye Lane,

Howrah, PIN:-711101, West Bengal

Date:

(Madhurima Das)

Contact this candidate