Venkata swamy S

#***, *** ***** *** ****

Koramangala 1st Block

E-mail: acfc80@r.postjobfree.com

Bangalore-560034

Phone (m): 808-***-****

Career Objective

I aspire to serve in an organization that gives an opportunity for

innovation with challenges and rich work culture thereby derive self

satisfaction while contributing to the growth of the organization.

Current Status

. Currently Working as Design Engineer VLSI in SATTVA eTECH India Pvt

Ltd. [Total experience 1.2 year].

. I completed Professional Development Training in VLSI System Design

and Verification from Sandeepani School of VLSI System Design,

Bangalore. [Training Duration 6 Months].

Technical Skills

Electronic Design Cadence(IUS82), Actel Libero IDE, Xilinx ISE and

Packages ModelSim.

Programming Languages Verilog HDL, VHDL, System Verilog and C.

FPGAs ProASIC3L, Spartan6

Protocols I2C, SPI, UART

Synthesis & Debugger Synplify Pro and Synopsis Identify Debugger and

Tektronix Logic Analyzer

Scripting TCL

Works carried out in MASTERS:

. VLSI Logic design - Design flow from RTL to GDS-II generation.

. Experience an EDA Tool

1. ANOLOG DESIGN

CADENCE (Virtuoso Analog Design Environment):

. Schematic Capture: S-Edit

. Physical Layout: L-Edit

. Analog Circuit Simulation using Spectre

. Physical Verification: Assura DRC, Assura LVS

2. DIGITAL DESIGN

. Simulation& Synthesis: CADENCE (NC-Sim, RTL Compiler)

. Basic Knowledge in SOC Encounter 9.1

Good Knowledge in Following:

. VLSI Logic design - Complete design flow from RTL to GDS-11.

. RTL coding in both Verilog & VHDL [FSM, Complex Data path/Control

Path Designs]

. Understanding the functional Requirements

. Creation and maintenance of design specification & documentation

. Block/System-Level Functional and logical Verification

. Logic Synthesis (using Design-Compiler or equivalent)

. Static Timing Analysis

. DFT Techniques

. Good Communication skills

Project Work

1. "IMPLEMENTATION AND VERIFICATION OF PROCESSOR AND NETWORK MODULE IOI

CONTROLLER (PRAN)".

Design Tool: Actel Libero IDE v9.1.

Debugger: Synopsys Identify Debugger, Model Sim.

Language: VHDL.

Role: Implementation of Processor and Network Module IOI Controller

(PRAN) and Verification of its functionality as per DO254.

Description: This Controller can be configured as Main or Standby, in

both the configuration it can communicates with Microprocessor MCF5485 -

Coldfire. IOI Controller can communicate with Input - Output Boards

using. The Interface between CPU and FPGA is through Flex bus and

interface between FPGA and IO boards is IO Bus Protocol.

PRAN High Level Architecture consist of

1 IO BUS Controller

2 Dual IOIM Controller

3 Battery Controller

4 LED Controller

5 RTC Controller - DS12R885

6 Temperature Sensor Controller - LM75A

7 Alphanumeric Display Controller - HCMS 2902

8 WDT Controller

2. "IMPLEMENTATION OF INTELLIGENT ANALOG INPUT MODULE (IAIM)".

Design Tool: Actel Libero IDE v9.1, Xilinx ISE v14.1.

Debugger: Synopsys Identify Debugger, Model Sim.

Language: VHDL.

Role: Implementation of intelligent Analog input module and

verification of its functionality as per DO254.

Description: IAIM is a module which has 32-analog input channels in

voltage mode. These channels acquire the analog inputs from external

source/field. The acquired analog inputs are converted into digital by

an ADC (AD-7654) and stored in the page module register which is in

FPGA. The CPU can scan these 32-channels individually/Continuously in

both the modes by sending a scan command and it can read the digital

data.

IAIM High Level Architecture consist of

1 EEPROM - AT24C02

2 Continuous Scan

3 Individual Scan

4 Page Module

5 Temperature Sensor Controller - LM75A

6 Alphanumeric Display Controller - HCMS 2902

3. "IMPLEMENTATION OF INTELLIGENT ANALOG OUTPUT MODULE-32 CHANNEL".

Design Tool: Actel Libero IDE v9.1.

Debugger: Synopsys Identify Debugger, Model Sim.

Language: VHDL

Role: Implementation of intelligent Analog output module (32-Channel)

and verification of its functionality as per DO254.

Description: This module will generate 32 analog outputs. All these

outputs will be voltage output signals in the range of 0-5V or 0-10V.

There shall be facility for setting 0-5V or 0-10V with the help of

jumpers for each channel. This module has to interface to CPU module

through IO Bus.

AOM-32 High Level Architecture consist of

1 EEPROM - AT24C02

2 DAC Controller (AD5382)

3 Page Module

4. "Implementation and Verification of 4*4 Time - Space Crossbar Switch".

Design Tool: Xilinx ISE v14.1, Model Sim SE 6.4a.

Language: Verilog HDL.

Role: Design and Verification of 4*4 Time Space Crossbar

Switch

Description: Switches are the basic building blocks of most

modern interconnections, aiming at providing data path

connectivity, while solving output contention, the major problem of

distributed multi-party communication. This uses a block priority to

solve a connection of exactly equal request. The first stage of the

switch is the time stages that interchange time slots between

external incoming digital channels and the subsequent space stage.

The space stage provides connectivity between time stages at the

input and output; it switches the frames according to the ports

address.

Education

Qualification Board/University Year of Passing Aggregate %

M-Tech (VLSI & Kakatiya University March 2012 80.12

Embedded Systems)

B-Tech JNTU Hyderabad July 2009 58.78

(Electronics &

Communication)

Intermediate Intermediate board April 2005 84.70

SSC SSC April 2003 74.20

Accomplishments

. Qualified in 2010 GATE Exam conducted by IIT Guwahati.

. Participated in A.P. State Chess open tournament held at Karimnager in

2004.

Subjects Learned in Masters

CMOS Analog Design, Mixed signal, Low-power Design using CMOS, DFT

Techniques and Advanced Digital design with HDLs.

Personal Profile

Father's Name : Shri Rayalingaiah Segyam

Date of Birth : 14 / 07 /1988

Present Address : #255, 4th Main, 4th cross,

Koramangal 1st Block, Bangalore

560034.

Languages known : Telugu, English, Hindi.

Nationality : Indian.

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