ARUN GATTADI

Address:

**-**-****, ***** *****

Mobile: +91-973******* Nizamabad - 503001

Email: acf938@r.postjobfree.com Andhra Pradesh

Professional Objective

To seek a challenging career and prove my excellence in that field by contributing my best to the

development of the organization.

Academic Records

Class/

Name of the Institution University Year of Percentage

Course

Pass out

B. Tech Vijay Institute of Technology And Jawaharlal Nehru Technological

2013 69.1

(ECE) Sciences University, Hyderabad

Kakatiya Junior Board of Intermediate

XII 2009 91.1

College Education, Andhra Pradesh

Kakatiya High Board of Secondary 84.3

X 2007

School Education, Andhra Pradesh

Skills Summary

Languages & Scripting & Tools VLSI ASIC Flow

• •

Verilog Cmos

• •

System Verilog Digital Design

• Perl • Verilog

• Cadence Virtuoso • System Verilog

• NC Sim

• FPGA

• RTL compiler

• Synthesis

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• •

Encounter DFT

• Place & Route

Technical Proficiency

• Post Graduate Diploma in VLSI Design & Technology at

Indian Institute of VLSI Design & Training – Bangalore, Karnataka

Six Month Full Time Course in VLSI Design based on Cadence flow.

Academic Projects

Design and implementation of fir filter by using radix-256 booth encoding algorithm

Description: A finite impulse response (FIR) filter computes its output using multiply and accumulate operations. In the present work,

a FIR filter based on novel higher radix-256 and RB arithmetic is implemented. The use of radix-256 booth encoding reduces the

number of partial product rows in any multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit.

PG diploma Projects

#1 Design of Synchronous FIFO using Verilog

Tools : NcSim, Simvision

Description: A FIFO is a circuit which gives output in the form of First in First Out i.e. the data which comes first at input is the first

one that goes out. Coding of FIFO was done by using Verilog language and after that Test Bench coding was done in Verilog and then

inputs were given in the Test Bench and output waveform was checked using simvision.

Roles & Responsibilities:

• Development of Verilog Code.

• Development of Test bench.

• Test cases to verify the functionality of the DUT.

#2 Design of APB Slave using System Verilog

Tools : NcSim, Simvision

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Description: An APB Slave is used for communicating low frequency bus used in SOC architecture. Coding of APB was done by

using Verilog language and after that Test Bench coding was done in System Verilog using one of the test methodology then inputs

were given in the Test Bench and output was checked using simvision.

Roles & Responsibilities:

• Development of Verilog Code.

• Development of System Verilog test bench environment.

• Test cases to verify the functionality of the DUT.

#3 FPGA - Design of Stop Watch

Tools : NcSim, Simvision, Xilinx FPGA.

Description: In this project a Stop Watch was designed using Verilog language. The Stop watch coded here will be able to keep time

till 10 min. It will be a 4 digit stopwatch counting from 0:00:0 till 9:59:9. The Stop Watch will be in the format H:MM:S

Roles & Responsibilities:

• Development of Verilog Code.

• Development of Test bench.

• Test cases to verify the functionality of the DUT.

• To Synthesize the Design and to generate the bitmap file for FPGA.

#4 Analog Design and Layout of PLL

Tools : Cadence virtuoso

Description: To draw schematic and Layout for the PLL.

Roles & Responsibilities:

• Draw the schematic for the design.

• To verify the characteristics of the design by using test schematic.

• To draw the layout for the design.

• To check the DRC, ERC & LVS errors.

#5 Physical Design & Verification of DTMF CHIP

Tools : Soc Encounter, RTL Compiler

Technology/ Layers : TSMC 0.18 micron / 6 Metal layers

Objective:

To do the synthesis, floor planning, Power planning, placement, CTS, Routing, Design signoff, Generating GDS II.

Roles & Responsibilities:

• Synthesising RTL code

• Placement for the Macro.

• Power planning to reduce IR Drop.

• Detail Routing & Timing analysis.

• To fix the DRC Violations using search & Repair.

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Personal details

Date of birth : 06-Sep-1992

Passport number : L6539014 until 10-Dec-2023

Father’s name : G. Srinivas

Marital status : Single

Languages known : English, Hindi and Telugu

DECLARATION:

I declare that the above information furnished by me is true and best of my knowledge.

Place :

Date : Signature

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