MANISH KUNDU

acf8zj@r.postjobfree.com

acf8zj@r.postjobfree.com

Mob: 978*******, 989-***-****

OBJECTIVE

I am an innovative, quick learner and hard working person, who have no problem to work in

team. I believe in proving my best in whatever responsibility that is entrusted to me and I make

sure that my work is completed in very professional manner. I am currently looking for an Entry

Level Job in Field of VLSI where I can make a significant contribution using sk ills I have

acquired.

AREA OF INTEREST

Digital Integrated Circuit Design

Digital Design

Physical Verification and layout Design

ASIC Design

Application

DFT (Design For Testability)

SKILL MATRIX

HDL Simulators: ModelSim, QuestaSim, ActiveHDL, RiveraPro.

FPGA Prototyping: Xilinx ISE 9.2i.

Circuit Simulators: Tanner13.1, Microwind (Layout Editor & DSCH)

Programming Languages: VHDL, Verilog, C and Perl (Beginner).

Operating Systems: Windows 8, 7, XP, Linux.

EDUCATION QUALIFICATION

M.Tech (VLSI Design) [2012-2014] from Maharishi Markandeshwar University,

Mullana, Haryana, with 8.52 CGPA (77%).

PG Diploma (VLSI Design) [2011-2012] from CDAC ACTS, Pune, with 72% (A Grade).

B.Tech (Hons.) Electronics and Communication [2007-2011] from Lovely Professional

University, Punjab, with 6.08 CGPA (54.72%).

10+2 [2007] from CBSE Board with 60%.

PROJECTS

[1] “Low Power SPI Protocol using Verilog”

SPI enables communication between a processor and peripherals in a SoC (System on

chip). My role was to design the Master and Slave of SPI protocol using Low Power RTL

coding techniques and achieved optimized device utilization. Moreover I have compared

my proposed work results with the Reference Paper results.

[2] “LVS-DRC of 4-Bit Vedic Multiplier/ 4-Bit Counter using 90nm technology”

Have designed the Schematic/Layout of both the design’s using Microwind tool by

following the Euler’s Path. The Scope of the Project was to check the DRC errors and

simulate the Layout and cross check the functionality of t he layout prepared using 90nm

technology.

[3] “I2C Bus Controller Using Verilog”

I2C (pronounced I-squared-C) allows communication of data between I2C devices over

two wires. It sends information serially using one line for data (SDA) and one for clock

(SCL).Basic Commands:. Send the START bit. Send the slave address. Send Read(R)-1 /

Write (W)-0 bit. Wait for/Send an acknowledge bit. Send/Receive the data byte (8bits).

Expect/Send acknowledge bit. Send the STOP bit. My role was to design the Master

part of I2c controller. I have used a Hook through which the whole I2c Operation will

take place. It is being used in the Master Part using a Start Signal. By using Hook we do

not need to force the other I/O. Simulated the functionality of the design and synthesized

it. Further implementation was done on FPGA Board.

INDUSTRIAL EXPOSURE

[1] 6 months Industrial Training in Central Electronics Limited (CEL), Ghaziabad, on

“Digital Axle Counter (Single and Multiple Section Digital Axle Counter)”

Axle counter is a train detecting equipment used in railways for monitoring a defined

track section to provide occupancy / clear status. The system detects the presence of a

train in any specified track Section. I designed a micro -controller logic board which

detects the presence (in) and exit (out) of train. When (in) count is equal to (out) count

the status is clear for next Train to come, if not equal then the track is occupied.

ACHIEVEMENTS

[1] Review Paper on SPI Protocol published in International Journal of VLSI Design and

Communication System.

[2] Research Paper on SPI Protocol published in International Journal of Research and

Innovative Technology. [Free Journal]

[3] Presented Paper on I2C protocol in National Conference held at M.M. University,

Mullana. Published Paper on I2C proto col in the Souvenir released by M.M. University,

Mullana.

PERSONAL DETAILS

S/O: Mr. Ajay Kundu

Address: 209/5, Central Town, Jalandhar (Punjab) 144001

Gender: Male

D.O.B: 31/08/1990

Languages: English, Hindi

Nationality: Indian

Declaration: I hereby declare that the information mentio ned above is true to best of my

knowledge.

Manish Kundu

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