RAHUL REDDY CHAMALA

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Mobile: 914-***-**** Email: acf8qj@r.postjobfree.com

ACADEMICS

Master of Science in Electrical and Computer Engineering GPA: 3.6/4.0

University of Florida, Gainesville, FL Aug 2012 – May 2014

.

Bachelor of Technology in Electronics and Communication Engineering GPA: 3.7/4.0

Osmania University College Of Engineering,Hyderabad,India Jul ’08 – May’12

Relevant Coursework: VLSI,AVLSI,VLSI Testing,Wireless Communications,DSP,Reconfigurable Computing,Computer

Architecture,Parallel Computer Architecture, Billion Transistor Computer Architecture(GPGPU), Principle Of Computer

System Design

SKILL SET

C,C++,Verilog,VHDL,System Verilog,Perl,Tcl,Cuda,Matlab,MPI,OpenMP

Programming Skills

Tools and Platforms Xilinx ISE,ModelSim,Xilinx Vivado,Cadence Spectre,Cadence Virtuoso

Altera Quartus,MATLAB,Keil,LabView

EXPERIENCE

CHREC Research Center, University of Florida May ’13 – Aug’13

Summer Intern

• I have worked as Research Intern in NSF center for high performance computing (CHREC) of University Of Florida

for performing functional verification,script development and documentation of ASIC and FPGA projects designed

from high level specifications to tapeout

PROJECTS

FPGA Implementation and Verification of 1D time convolution using Dimetalk Software Feb 2014

• An implementation of ID time convolution on Nallatech FPGA board in RTL using pipelined datapath and smart

buffers with synchronization of data in different clock domains(metastability) and verified with testbenches based on

assertion and constrained random verification

Low Power Implementation Of 16 bit RISC CPU Dec 2013

• Designed a 16 bit RISC CPU in RTL(Verilog) and performed Synthesis and Place and Route in Cadence and

obtained a netlist with DRC and LVS match.Clock gating is used as power saving technique

Compact test pattern Generator (ATPG) Mar’13-Apr’13

• Built a compact test generating program (ATPG) in Perl which takes a .v netlist and generates test vectors to identify

all stuck at faults

Designing,RTL Implementation and Verification Of Asynchronous FIFO in Verilog Mar’13-Apr’13

• An 8 bit wide, 16 words deep asynchronous FIFO is designed with FPGA registers as memory and binary to gray

code pointers are used along with Dual Flip Flop synchronizers to control metastability

Predicting Turbulent Flow Field using ANN on CPU-GPU platform Dec 2012

• Neural network is designed to predict the next time frame outputs of the flow field based on the present inputs.It is

parallelized on Nvidia Tesla S1070 in cuda,mpi and opemp with a speedup improvement of 8

Power Optimization Using Software Prefetching in GPU Nov 2012

• Software Prefetching is performed on Cuda benchmarks on Nvidia Tesla which results in increased performance and

power optimization is performed using frequency scaling down technique under performance constraint

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