PAVAN VERNEKAR
Address: W-**, Malleshwaram *rd cross, Bangalore-
M.S. Graduate
VLSI-CAD Engineering 560003, Karnataka, India
School of Information Science, Manipal Phone: +91-966*******
Email: acf76w@r.postjobfree.com
Career Objective
Seeking for a position of VLSI Engineer where I can show my leadership and technical skills and have opportunities
for personal growth and development.
Areas of Interest
RTL Coding and Simulation Constraints Generation and RTL Synthesis
Timing Analysis Peripheral Interfacing to Processor
Memory Interfacing to Processor Rapid FPGA Prototyping and Advanced Debugging
Professional Experience
Six Months of Experience in front-end designing using RTL coding by undergoing "Advanced FPGA"
course at IETE.
Educational qualification
Year of Marks%
Class/Course Name of Institute Board/University
Passing /CGPA
Manipal Academy of Higher
MS School of Information
2013 8.72 CGPA
(VLSI-CAD) Science, Manipal. Education (MAHE), Manipal
BE
KNS Institute of Visweshwaraiah Technological
(Electronics & 2010 67.89%
Technology, Bangalore. University,
communication)
JSS PU College,
PUC Karnataka PU Board 2006 70.83%
Dharwad.
Basel Mission English
Karnataka Secondary Education
SSLC Medium High School, 2004 79.20%
Board
Dharwad.
Internship Project
1) “DESIGN AND IMPLEMENTATION OF PROCESSOR INTERFACE
LOGIC IN FPGA FOR MIL-STD-1750A-MICROPROCESSOR”
Company: Indian Space Research Organization (ISRO)
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Project Duration Experience: 1 Year (October-2012 – September-2013)
Processor: MIL-STD-HX1750A (16-bit)
Project Aim: Porting discrete ICs (used for Memory/Peripheral interfacing to CPU) into a single
high density reprogrammable FPGA design for quick turnaround time as well as to reduce board -
space.
Project Summary:
Integrated the logics of different discrete ICs into a single RTL design.
Redesigned and modified memory interface aimed at
1. Expanding the addressing space capability using MMU.
2. Accommodating slower/faster Memory using parameterized Wait-State Logic.
Design Flow Adopted as: Requirement Capture -> RTL Coding -> Simulation -> Constraints ->
Synthesis -> Timing Analysis -> Automatic Place and Route -> FPGA Fusing.
Interface Logics Designed as follows:
I. Design of Memory Management Unit (MMU)
The MA31751 is an Interface device designed to increase the memory addressing capability of the
HX1750 CPU. It is mainly concerned with the design of memory and its addressing logic.
II. Design of Wait State Logic
Wait state logic was designed so as to match the processor speed with that of the memory speed, as
we know memory transfer speed is slow as compared to the processor sp eed so to overcome this
state the wait state logic was implemented.
III. Design of 16-Bit Parallel Error Detection & Correction(EDAC) Logic
The EDAC generates a 6-bit check word from each 16-bit data word. The check word is stored with
the data word during a memory write cycle. During memory read cycle a 22-bit word is taken from
memory and checked for errors.
IV. Design of Arbitration Logic for 1553 bus
The Arbiter was designed to act as an Interface Controller between the CPU and the master 1553
bus. Based on the BUS req, grant, ack, busy and full signals the communication and data transfers
takes place in 1553 RAM.
V. Design of EEPROM Interface logics
The EEPROM Interface logic board containing IO decoder, Supply control logic, IO latches for
address, data and control bus was completely replaced into RTL code, simulated, synthesized and
then was fused into FPGA.
Academic Projects
1) “Implementation Of Physical Layer of PCI-Express”
M.S. Mini Project:
My prime responsibility included RTL coding, The transmit logic of the physical layer processes
data packets received from the data link layer then converts them into a serial bit stream, this bit stream is
then clocked out at the lane on to the link.The receiver logic clock in the serial bit stream arriving on lanes
and converts it to parallel symbols stream, processes this stream and sends it to the data lin k layer of the
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receiver. Simulation of the PCI-Express protocol(Physical Layer) was carried using Verilog, VCS and
Xilinx ISE.
2) “Home And Office Surveillance And Automation Robot”
B.E. Final Year Project:
This autonomous robot navigates along the wall and measures the parameter at every specific point. It
measures various parameters such as temperature, light, humidity, smoke, LPG, motion etc.
Based on the sensed values the robot issues control signals to the control unit and hence performs the
needful controlling action.
Professional Course
Pursued “Advanced FPGA” Course from Institute of Electronics and Telecommunication Engineers
(IETE), Bangalore, With a duration of 6 months (February-2014 – July-2014).
Design Flow Implementation: RTL Coding, Simulation, Synthesis, Timing Analysis, Place and Route,
Signal Tap II Logic Analyzer, FPGA Prototyping.
Description:
My prime responsibility included RTL coding of RAM, ROM and other basic combinational and
sequential logics with few instantiation done using IP catalog and is implemented using VHDL in Quartus
II Environment, RTL simulation was carried out using Modelsim, the design is synthesized and the pin
planning was done and the design is fed into the Signal tap II logic analyzer to check the Onchip
simulation after this the FPGA(Altera Cyclone IV FPGA) prototyping was done on the DE0 Nano board
and observed the required output.
Technical Skills
Operating System : LINUX Red Hat 8, WINDOWS XP/Vista/7/10.
Languages : VHDL, VERILOG, C.
Scripting Languages : PERL.
Design Tools : Xilinx, VCS, Quartus II, Magic, BSPICE, HSPICE.
Simulation Tools : ISE Simulator, Modelsim.
Synthesis Tools : XST, Synplify.
Seminars
Fabrication of PCB Manually
Sensors and its Applications
Declaration
I hereby declare that the information furnished above is true to the best of my knowledge.
Place:
Date: PAVAN VERNEKAR
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