Rangani Jaydeep Bhagvanjeebhai

DOB: September *2, 1990

Email:acf3sy@r.postjobfree.com

Mo: +919*********

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Address: #**, * *****, ******* ***** Bldg, Near Oxford

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College, J.P. Nagar, 1 Phase, Bangalore -560078.

Education

Degree University/Institute Year CPI/Aggregate

M.Tech. (VLSI & Dhirubhai Ambani Institute of Information and 2012-14 8.11

Embedded System) Communication Technology (DA-IICT),

Gandhinagar, Gujarat.

B.E.(E.C.) Government Engineering College, Rajkot(Gujarat). 2007-11 65.95%

Intermediate/+2 Sardar Patel Vidhyamandir, Rajkot (Gujarat) 2006-07 79%

GSHSEB (Gujarat Secondary and Higher Secondary

Education Board).

High School Sardar Patel Vidhyamandir, Rajkot (Gujarat) 2004-05 76.43%

GSHSEB.

Skills

Areas of Interest VLSI Design, Low power VLSI Design, VLSI Subsystems Design.

Programming Languages Perl, Shell Scripting, Verilog, VHDL, C, C++.

Tools ASIC, Cadence, Cadence Virtuoso, Xilinx, SoC, FPGA, Modelsim, MATLAB, LT spice,

Code Blocks, LaTeX, Silos, Logisim.

Technical Electives Digital System Architecture, VLSI Design.

Projects

HDL Implementation of Associative Memory Based Instruction Predictor for Power (June, 2013 – July,2014)

Reduction Team Size - 1

Guide : Prof. Mazad Zaveri

Thesis: The goal is to reduce power, by assuming the circuit is divided in different

power consuming modules, observing operation of these modules and selectively

turning on/off these modules. We propose to use AM (Associative Memory) for

selectively turning on/off these modules, based on the statistics of operation of

these modules. We have used AM (Associative Memory) algorithm for power

reduction.

Power Analysis Tool (October, 2013 –November,2013)

Guide:Prof. Biswajit Mishra Team Size - 2

C++ program that mimics a power analysis tool: The program inputs a .vcd file and .v

file and counts the number of transition. Power analyse based on transition and

output capacitance.

Low Power Low pass FIR Filter (September,2013-October,2013)

Guide : Prof. Biswajit Mishra Team Size - 2

We design adder and multiplier using specific library for possible low power

consumption.

Optimal Supply and Threshold Scaling for CMOS Circuits ( August,2013-September,2013)

Guide : Prof. Biswajit Mishra Team Size - 1

To find constant energy and delay contours for varying activity factor in the circuit

for 350nm and 180nm technology. Observe the Optimal Vdd - Vth operating points

for the worst case energy.

Text Message Entry Design (September,2013-October,2013)

Guide : Prof. Biswajit Mishra Team Size -1

Design a text message entry system using VHDL in Xilinx. The number keys resemble

a mobile key pad.

Implementing Computer Arithmetic (January, 2013 – March, 2013)

Guide: Prof. Mazad Zaveri Team Size -2

Cordic Equation: For calculating trigonometric Functions. Implement Pipeline

structure of circular CORDIC (vectoring mode) in Verilog.

Radix-8 Booth Multiplier: Sequential and parallel implementation in Verilog.

Adders: Speed, area and power Comparison of different Adders in LTspice.

Verilog Implementation for Vender Machine and a 5 Tap FIR Filter (January, 2013 – March, 2013)

Guide: Prof. Rahul Dubey Team Size -1

To create a Verilog code in Xilinx for both Finite State Machine (Vender) and FIR Filter

and to implement a FSM for a Vender Machine on STK500(microcontroller) kit.

Room Automation (January, 2011 – May, 2011)

Guide : Prof. C H Vithlani Team Size -2

Controlling equipment like fan, tube light, door using microcontroller 8052 with the

help of ADC (Analog to Digital Converter) IC, LM 35(Temperature Sensor), Relay,

Proximity Sensor.

Positions of Responsibility

Teaching Assistant, Embedded Hardware Design (August, 2012,’13 –

November, 2012,’13)

Teaching Assistant, Analog Circuit (January, 2013,’14 – April, 2013,’14)

Head Teaching Assistant in Analog Circuit lab (January, 2014 – April, 2014)

Achievement

Gate 2012 All India Rank – 2293 with GATE score 579

Interests and Hobbies

Dandiya Rass, Playing badminton, Swimming, Playing Basketball.

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